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multi-channel ic 34704 ordering information device temperature range (t a ) package mc34704aep/r2 -20c to 85c 56 qfn ep mc34704bep/r2 ep suffix (pb-free) 98asa10751d 56-pin qfn freescale semiconductor, inc. reserves the right to change the detail specifications, as may be required, to permit improvements in the design of its products. document number: mc34704 rev. 5.0, 2/2011 freescale semiconductor technical data ? freescale semiconductor, inc., 2008 - 2011. all rights reserved. multiple channel dc-dc power management ic the 34704 is a multi-channel power management ic (pmic) used to address power management needs for various multimedia application microprocessors. its ability to provide either 5 or 8 independent output voltages with a single input power supply (2.7 and 5.5 v) together with its high efficien cy, make it ideal for portable devices powered up by li-ion/polymer batteries or for usb powered devices as well. the 34704 is housed in a 7x7 mm, pb-free, qfn56 and is capable of operating at a switching frequency of up to 2.0 mhz. this makes it po ssible to reduce external component size and to implement full space efficient power management solutions. features ? 8 dc/dc (34704a) or 5 dc/dc (34704b) switching regulators with up to 2% output voltage accuracy ? dynamic voltage scaling on all regulators. ? selectable output voltage or current regulation on reg8 ?i 2 c programmability ? output under-voltage and over-voltage detection for each regu lator ? over-current limit detection and short-circuit protection for each regu lator ? thermal limit detection for each regulator, except reg7 ? integrated compensation for reg1, reg3, reg6, and reg8 ?5.0 a maximum shutdown current (all regulators are off, 5.5 v vin) ? true cutoff on all of the boo st and buck-boost regulators ? pb-free packaging designated by suffix code ep mpu ddr memory v core v io1 v io2 v ddr v bkl lcd +5v vref+ (5 to 16v) vref- (-5 to -9v) 34704a/b * available only in 34704a device reg 8 reg 4 reg 3 reg 2 reg 5 *reg 1 *reg 6 *reg 7 pgnd i 2 c comm gnd gnd figure 1. 34704 simplified application diagram
analog integrated circuit device data 2 freescale semiconductor 34704 device variations device variations table 1. device variations orderable part number no. of regulators regulator number mc34704aep/r2 8 reg 1 - 8 mc34704bep/r2 5 reg 2, 3, 4, 5, 8
analog integrated circuit device data freescale semiconductor 3 34704 internal block diagram internal block diagram out8 sw8 bt8 fb8 out7 drv7 fb7 vref7 comp7 vout6 sw6 bt6 fb6 bt5d pvin5 sw5d vout5 sw5u bt5u fb5 comp5 vddi scl sda rst vin agnd vg bt1 bt2d pvin2 sw2d vout2 sw2u bt2u fb2 comp2 bt3 pvin3 sw3 vout3 bt4d pvin4 sw4d vout4 sw4u bt4u fb4 comp4 onoff lion freq ss pgnd (expad) boot predrv vg control vout1 (34704a) sw1 pwm error amp reg8 voltage data boot predrv vg control pwm p-skip error amp reg4 voltage data predrv boot vg control pwm p-skip error amp reg3 voltage data predrv boot vg fb3 boot predrv vg control pwm p-skip error amp reg2 voltage data predrv boot vg uvlo detection thermal detection adc mux startup control vin boot predrv vg control pwm p-skip error amp start-up ipeak-det and blanking sw control reg1/vg voltage data l error amp predrv control pwm error amp voltage data reg7 (34704a) amp boot predrv vg control pwm error amp reg6 (34704a) voltage data l error amp boot predrv vg control pwm p-skip error amp reg5 voltage data predrv boot vg vddi (2.5v) vddimon (vddidet) vg i 2 c registers reset driver sequencer soft start osc/divider to reg 1-8 figure 2. 34704 internal block diagram
analog integrated circuit device data 4 freescale semiconductor 34704 pin connections pin connections 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 42 41 40 39 38 37 36 35 34 33 32 31 30 29 56 55 54 53 52 51 50 49 48 47 46 45 44 43 57 exposed pad pgnd bt5u bt4d pvin4 sw4d vout4 sw4u bt4u fb4 comp4 bt3 pvin3 sw3 vout3 fb3 ss freq fb8 bt8 vout8 sw8 sw1 vg vout1 bt1 scl sda rst comp7 bt2u onoff lion vddi vin agnd vout6 sw6 bt6 fb6 vout7 drv7 fb7 vref7 comp5 fb5 bt5d pvin5 sw5d vout5 sw5u sw2u vout2 sw2d pvin2 bt2d fb2 comp2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 42 41 40 39 38 37 36 35 34 33 32 31 30 29 56 55 54 53 52 51 50 49 48 47 46 45 44 43 57 exposed pad pgnd bt5u bt4d pvin4 sw4d vout4 sw4u bt4u fb4 comp4 bt3 pvin3 sw3 vout3 fb3 ss freq fb8 bt8 vout8 sw8 sw1 vg nc0 bt1 scl sda rst nc1 bt2u onoff lion vddi vin agnd pgnd5 pgnd4 nc4 agnd3 pgnd2 nc3 agnd1 nc2 comp5 fb5 bt5d pvin5 sw5d vout5 sw5u sw2u vout2 sw2d pvin2 bt2d fb2 comp2 34704a 34704b figure 3. 34704 pin connections table 2. 34704 pin definitions a functional description of each pin can be found in the functional pin description section beginning on page 17 . pin number device pin name pin function formal name definition 1 a/b bt5u passive reg5 boost stage bootstra p capacitor input pin connect a 1.0 f capacitor between this pin and sw5u pin to enhance the gate of the switch power mosfet. 2 a/b bt4d passive reg4 buck stage bootstra p capacitor input pin connect a 0.01 f capacitor between this pin and sw4d pin to enhance the gate of the switch power mosfet. 3 a/b pvin4 power reg4 power supply input vol tage this is the connection to the drai n of the high side switch fet. input decoupling /filtering is required for proper reg4 operation. use a 10uf decoupling capacitor for better performance. 4 a/b sw4d input/output reg4 buck stage swit ching node the inductor is connected between this pin and the sw4u pin. 5 a/b vout4 output reg4 regulated output voltag e pin connect this pin to the load and to the output filter as close to the pin as possible. 6 a/b sw4u input/output reg4 boost stage swit ching node the inductor is connected between this pin and the sw4d pin. 7 a/b bt4u passive reg4 boost stage bootstra p capacitor input pin connect a 0.01 f capacitor between this pin and sw4u pin to enhance the gate of the switch power mosfet. 8 a/b fb4 input reg4 voltage feedback input for voltage regulation/programming connect the feedback resistor d ivider to this pin. 9 a/b comp4 passive reg4 compensation netwo rk connection reg4 compensation network connection. 10 a/b bt3 passive reg3 bootstrap capacitor input pin connect a 0.01 f capacitor between this pin and sw3 pin to enhance the gate of the switch power mosfet.
analog integrated circuit device data freescale semiconductor 5 34704 pin connections 11 a/b pvin3 power reg3 power supply input voltage this is the connection to the drai n of the high side switch fet. input decoupling /filtering is required for proper reg3 operation. use a 10uf decoupling capacitor for better performance. 12 a/b sw3 output reg3 switching node the inductor is connected between this pin and the regulated reg3 output. 13 a/b vout3 output reg3 output voltage return pin this is the discharge path of reg3 output voltage. 14 a/b fb3 input reg3 voltage feedback input for voltage regulation/programming connect the feedback resistor divider to this pin. 15 a/b ss input soft start time the soft start time for all regulators can be adjusted by connecting this pin to an exter nal resistor divider between vddi and agnd pins. 16 a/b freq input oscillator frequency the oscillator frequency can be adj usted by connecting this pin to an external resistor divide r between vddi and agnd pins. this pin sets f sw1 value. 17 a/b fb8 input reg8 voltage feedback input for voltage regulation/programming connect the feedback resistor divider to this pin. 18 a/b bt8 passive reg8 bootstrap capacitor input pin connect a 0.01 p f capacitor between this pin and sw8 pin to enhance the gate of the synchronous power mosfet. 19 a/b vout8 output reg8 regulated output voltage pin connect this pin directly to the load directly and to the output filter as close to the pin as possible. 20 a/b sw8 output reg8 switching node the inductor is connected between this pin and the vin pin. 21 a/b sw1 output reg1 switching node the inductor is connected between this pin and the vin pin. 22 a/b vg passive reg1 regulated output voltage before the cutoff switch reg1 regulated output voltage before the cut-off switch. this supplies the internal circuits and the gate drive 23 (1) a vout1 output reg1 regulated output voltage pin. connect this pin directly to the load directly and to the output filter as close to the pin as possible. b nc0 no connect - pin 23 is not connected. 24 a/b bt1 passive reg1 bootstrap capacitor input pin connect a 1.0 p f capacitor between this pin and sw1 pin to enhance the gate of the switch power mosfet. 25 a/b scl input/output i 2 c serial interface clock input i 2 c serial interface clock input. 26 a/b sda input/output i 2 c serial interface data input i 2 c serial interface data input. 27 a/b rst open drain power reset output signal (microprocessor reset) this is an open drain output and must be pulled up by an external resistor to a supply voltage like v in . 28 a comp7 passive reg7 compensation network connection reg7 compensation network connection. b nc1 no connect - pin 28 is not connected 29 a vref7 output reg7 resistor feedback network reference voltage connect this pin to the bottom of the feedback resistor divider. b nc2 no connect - pin 29 is not connected table 2. 34704 pin de finitions (continued) a functional description of each pin can be found in the functional pin description section beginning on page 17 . pin number device pin name pin function formal name definition
analog integrated circuit device data 6 freescale semiconductor 34704 pin connections 30 a fb7 input reg7 voltage feedback input for voltage regulation/programming connect the feedback resistor divider to this pin. b agnd1 - - pin 30 is connected to agnd 31 a drv7 output reg7 external power mosfet gate drive reg7 external power mosfet gate drive. b nc3 no connect - pin 31 is not connected 32 a vout7 output reg7 output voltage return pin. this is the discharge path of reg7 output voltage. b pgnd1 - - pin 32 is connected to pgnd 33 a fb6 input reg6 voltage feedback input for voltage regulation/programming connect the feedback resistor divider to this pin. b agnd2 - - pin 33 is connected to agnd 34 a bt6 passive reg6 bootstrap capacitor input pin. connect a 0.01 p f capacitor between this pin and sw6 pin to enhance the gate of the synchronous power mosfet. b nc4 no connect - pin 34 is not connected 35 a sw6 output reg6 switching node the inductor is connected between this pin and the vin pin. b pgnd2 - - pin 35 is connected to pgnd 36 a vout6 output reg6 regulated output voltage pin connect this pin directly to the load directly and to the output filter as close to the pin as possible. b pgnd3 - - pin 36 is connected to pgnd 37 a/b agnd ground analog ground of the ic analog ground of the ic. 38 a/b vin power battery voltage connection input decoupling /filtering is required for the device to operate properly. 39 a/b vddi output internal supply voltage connect a 1.0 p f low esr decoupling filter capacitor between this pin and gnd. 40 a/b lion input battery detection always pull this pin high with a 470kohm resistor to indicate input power is present. 41 a/b onoff input dual function ic turn on/ off this is a hardware enable/dis able for the 34704a/b. it can be connected to a mechanical switch to turn the power on or off. 42 a/b bt2u passive reg2 boost stage bootstrap capacitor input pin connect a 1.0 p f capacitor between this pin and sw2u pin to enhance the gate of the switch power mosfet. 43 a/b comp2 passive reg2 compensation network connection reg2 compensation network connection. 44 a/b fb2 input reg2 voltage feedback input for voltage regulation/programming connect the feedback resistor divider to this pin. 45 a/b bt2d passive reg2 buck stage bootstrap capacitor input pin connect a 1.0 p f capacitor between this pin and sw2d pin to enhance the gate of the switch power mosfet. 46 a/b pvin2 power reg2 power supply input voltage this is the connection to the drai n of the high side switch fet. input decoupling /filtering is required for proper reg2 operation. use a 10uf decoupling capacitor for better performance table 2. 34704 pin de finitions (continued) a functional description of each pin can be found in the functional pin description section beginning on page 17 . pin number device pin name pin function formal name definition
analog integrated circuit device data freescale semiconductor 7 34704 pin connections 47 a/b sw2d input/output reg2 buck stage switching node the inductor is connected between this pin and the sw2u pin. 48 a/b vout2 output reg2 regulated output voltage pin connect this pin to the load and to the output filter as close to the pin as possible. 49 a/b sw2u input/output reg2 boost stage switching node the inductor is connected between this pin and the sw2d pin. 50 a/b sw5u input/output reg5 boost stage switching node the inductor is connected between this pin and the sw5d pin. 51 a/b vout5 output reg5 regulated output voltage pin connect this pin to the load and to the output filter as close to the pin as possible. 52 a/b sw5d input/output reg5 buck stage switching node the inductor is connected between this pin and the sw5u pin. 53 a/b pvin5 power reg5 power supply input voltage this is the connection to the drai n of the high side switch fet. input decoupling /filtering is required for proper reg5 operation. use a 10uf decoupling capacitor for better performance 54 a/b bt5d passive reg5 buck stage bootstrap capacitor input pin connect a 1.0 p f capacitor between this pin and sw5d pin to enhance the gate of the switch power mosfet. 55 a/b fb5 input reg5 voltage feedback input for voltage regulation/programming connect the feedback resistor divider to this pin. 56 a/b comp5 passive reg5 compensation network connection reg5 compensation network connection. exposed pad a/b pgnd ground power ground connection for all of the regulators except reg7 power ground connection for all of the regulators except reg7. this pad is provided to enhance thermal performance. notes 1. if regulator 1 is not used, leave pin 23 unconnected, all other components shoul d be used to provide vg to the system 2. if regulators 5, 6, 7 and 8 are not used, connect the corresponding pins as follows: fb node: tied to gnd, bt node: not conne cted, vout node: tied to gnd, sw node: tied to gnd, drv node: tied to gnd (reg7 only), comp pin: not conne cted, pvin pin: not connected. 3. reg 2,3 and 4 should always be populated. table 2. 34704 pin de finitions (continued) a functional description of each pin can be found in the functional pin description section beginning on page 17 . pin number device pin name pin function formal name definition
analog integrated circuit device data 8 freescale semiconductor 34704 electrical characteristics maximum ratings electrical characteristics maximum ratings table 3. maximum ratings all voltages are with respect to ground unless otherwise no ted . exceeding these ratings may cause a malfunction or permanent damage to the device. ratings symbol value unit electrical ratings battery input supply voltage (vin) pin pvinx, rst , onoff , lion, drv7 (8) , vg, scl, sda and vout1-5 pins vddi, compx, fbx, vref7 (8) , freq, and ss pins v in -0.3 to 6.0 -0.3 to 6.0 -0.3 to 3.0 v sw1-5 pins v sw-low -1.0 to 6.0 v sw8, sw6 (8) pins v sw-high -1.0 to 27 v btx pins (referenced to switch node) v bt -v sw -0.3 to 6.0 v btx pins to gnd v bt -0.3 to 27 v vout8, vout6 (8) pins v out-high -0.3 to 27 v vout7 pin (8) v out-neg -10.0 to 0.3 v continuous output current reg1 (8) reg2,5 reg3 reg4 reg6,7 (8) reg8 500 500 550 300 60 30 ma esd voltage human body model charge device model v esd1 v esd2 1000 500 v thermal ratings maximum junction temperature t j(max) +150 c storage temperature t stg -65 to +150 c maximum power dissipation (t a = 85c) pd 2.5 w thermal resistance (7) thermal resistance junction to ambient junction to board r ja r jb 26 10 c/w peak package reflow temperature during reflow (5) , (6) t pprt note 6 c notes 4. esd testing is performed in accordanc e with the human body model (hbm) (c zap = 100 pf, r zap = 1500 ), and the charge device model (cdm), robotic (c zap = 4.0 pf). 5. pin soldering temperature limit is for 10 seconds maximum dura tion. not designed for immersion so ldering. exceeding these lim its may cause malfunction or permanent damage to the device. 6. freescale?s package reflow capability m eets p b-free requirements for jedec standard j-std-020c. for peak package reflow temperature and moisture sensitivity levels (msl), go to www.free scale.com, search by par t number [e.g. remove prefixes/suffixe s and enter the core id to view all orderable parts. ( i.e. mc33xxxd enter 33xxx), and review parametrics. 7. thermal resistance is based on a four-layer board (2s2p) 8. available only on the 34704a
analog integrated circuit device data freescale semiconductor 9 34704 electrical characteristics static electrical characteristics static electrical characteristics table 4. static electric al characteristics characteristics noted under conditions 2.7 v d v in d 5.5 v, - 20 q c d t a d 85 q c, gnd = 0 v, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit power input input supply voltage typical range v in 2.7 - 5.5 v input dc supply current (9) vin pin only all regulators are on, no load; v in = 3.6 v, fsw =1.0 mhz regulators 1 - 5 on, reg 6, 7 and 8 off; v in = 3.6 v, fsw = 1.0 mhz i in - - - - 86 32 - - - ma input dc shutdown supply current (9) (shutdown, all regulators are off and v in = 5.5v) this includes any pin connected to the battery i off - - 5.0 p a rising uvlo threshold uvlo r - - 3.0 v falling uvlo threshold uvlo f - - 2.7 v rst rst low level output voltage i ol = 1.0 ma v rst-ol - - 0.4 v rst leakage current, off-state @ 25c i rst-lkg - - 1.0 ma current limit monitoring over and short-circuit current limit accuracy - -20 - 20 % regulator 1 & vg vg output voltage v vg - 5.0 - v reg1 output voltage (10) v out - 5.0 - v output accuracy - -4.0 - 4.0 % line/load regulation (9) reg ln/ld -1.0 - 1.0 % dynamic voltage scaling range v dyn -10 - 10 % dynamic voltage scaling step size v dyn_step - 2.5 - % continuous output current (9) i out - 100 500 ma over-current limit (detected in low side fet) i lim_ion - 2.7 - a short-circuit current limit (detected in the blocking fet) i short_ion - 4.0 - a over-current limit accuracy - -20 - 20 % n-ch switch power mosfet r ds(on) r ds(on) - sw - 100 - m : n-ch synch. power mosfet r ds(on) r ds(on) - sy - 150 - m : n-ch shutdown power mosfet r ds(on) r ds(on) - sh - 100 - m : discharge mosfet r ds(on) r ds(on) - dis - 70 - : thermal shutdown threshold (9) t sd - 170 - c thermal shutdown hysteresis (9) t sd-hys - 25 - c sw1 leakage current (off state) @ 25c i sw1_lkg - - 1.0 p a peak current detection threshold at power up (9) i peak - 300 - ma notes: 9. guaranteed by design 10. available only on the 34704a
analog integrated circuit device data 10 freescale semiconductor 34704 electrical characteristics static electrical characteristics regulator 2 output voltage range v out 0.6 3.3 3.6 v output accuracy - -2.0 - 2.0 % line/load regulation (11) reg ln/ld -1.0 - 1.0 % feedback reference voltage v fb - 0.600 (12) - v dynamic voltage scaling range v dyn -17.5 - 17.5 % dynamic voltage scaling step size v dyn_step - 2.5 - % continuous output current (11) i out - 200 500 ma over-current limit (detected in buck high side fet) i lim_ion - 1.4 - a short-circuit current limit (detected in buck high side fet) i short_ion - 2.1 - a battery over-current limit accuracy - -20 - 20 % n-ch buck switch power mosfet r ds(on) r ds(on) - sw - 120 - m : n-ch buck synch. power mosfet r ds(on) r ds(on) - sy - 1000 - m : n-ch boost switch power mosfet r ds(on) r ds(on) - sw - 120 - m : n-ch boost synch. power mosfet r ds(on) r ds(on) - sy - 120 - m : discharge mosfet r ds(on) r ds(on) - dis - 70 - : thermal shutdown threshold (11) t sd - 170 - c thermal shutdown hysteresis (11) t sd-hys - 25 - c pvin2 leakage current (off state) @25c i pvin2g_lkg - - 1.0 p a sw2d leakage current (off state) @25c i sw2d_lkg - - 1.0 p a sw2u leakage current (off state) @25c i sw2u_lkg - - 1.0 p a regulator 3 output voltage range v out 0.6 1.2 1.8 v output accuracy - -4.0 - 4.0 % line/load regulation (11) reg ln/ld -1.0 - 1.0 % feedback reference voltage v fb - 0.600 (12) - v dynamic voltage scaling range v dyn -17.5 - 17.5 % dynamic voltage scaling step size v dyn_step - 2.5 - % continuous output current (11) i out - 150 550 ma over-current limit (detected in buck high side fet) i lim_ion - 1.0 - a short-circuit current limit (detected in buck high side fet) i short_ion - 1.5 - a over-current limit accuracy - -20 - 20 % n-ch switch power mosfet r ds(on) r ds(on) - sw - 500 - m : n-ch synch. power mosfet r ds(on) r ds(on) - sy - 500 - m : discharge mosfet r ds(on) r ds(on) - dis - 70 - : thermal shutdown threshold (11) t sd - 170 - c thermal shutdown hysteresis (11) t sd-hys - 25 - c pvin3 leakage current (off state) @25c i pvin3_lkg - - 1.0 p a sw3 leakage current (off state) @25c i sw3_lkg - - 1.0 p a notes: 11. guaranteed by design 12. v fb is 0.6v when the part ist powered up and no d vs is changed. dvs is ac hieved by modifying v fb reference. table 4. static electrical characteristics (continued) characteristics noted under conditions 2.7 v d v in d 5.5 v, - 20 q c d t a d 85 q c, gnd = 0 v, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 11 34704 electrical characteristics static electrical characteristics regulator 4 output voltage range v out 0.6 1.8 3.6 v output accuracy - -2.0 - 2.0 % line/load regulation (13) reg ln/ld -1.0 - 1.0 % feedback reference voltage v fb - 0.600 (14) - v dynamic voltage scaling range v dyn -10 - 10 % dynamic voltage scaling step size v dyn_step - 1.0 - % continuous output current (13) i out - 100 300 ma over-current limit (detected in buck high side fet) i lim_ion - 1.5 - a short-circuit current limit (detected in buck high side fet) i short_ion - 2.25 - a over-current limit accuracy - -20 - 20 % n-ch buck switch power mosfet r ds(on) r ds(on) - sw - 200 - m : n-ch buck synch. power mosfet r ds(on) r ds(on) - sy - 600 - m : n-ch boost switch power mosfet r ds(on) r ds(on) - sw - 200 - m : n-ch boost synch. power mosfet r ds(on) r ds(on) - sy - 600 - m : discharge mosfet r ds(on) r ds(on) - dis - 70 - : thermal shutdown threshold (13) t sd - 170 - c thermal shutdown hysteresis (13) t sd-hys - 25 - c pvin4 leakage current (off state) @25c i pvin4_lkg - - 1.0 p a sw4d leakage current (off state) @25c i sw4d_lkg - - 1.0 p a sw4u leakage current (off state) @25c i sw4u_lkg - - 1.0 p a regulator 5 output voltage range v out 0.6 3.3 3.6 v output accuracy - -2.0 - 2.0 % line/load regulation (13) reg ln/ld -1.0 - 1.0 % feedback reference voltage v fb - 0.600 (14) - v dynamic voltage scaling range v dyn -17.5 - 17.5 % dynamic voltage scaling step size v dyn_step - 2.5 - % continuous output current (13) i out - 150 500 ma over-current limit (detected in buck high side fet) i lim_ion - 1.4 - a short-circuit current limit (detected in buck high side fet) i short_ion - 2.1 - a over-current limit accuracy - -20 - 20 % n-ch buck switch power mosfet r ds(on) r ds(on) - sw - 120 - m : n-ch buck synch. power mosfet r ds(on) r ds(on) - sy - 1000 - m : n-ch boost switch power mosfet r ds(on) r ds(on) - sw - 120 - m : n-ch boost synch. power mosfet r ds(on) r ds(on) - sy - 120 - m : discharge mosfet r ds(on) r ds(on) - dis - 70 - : thermal shutdown threshold (13) t sd - 170 - c thermal shutdown hysteresis (13) t sd-hys - 25 - c notes: 13. guaranteed by design 14. v fb is 0.6v when the part ist powered up and no d vs is changed. dvs is ac hieved by modifying v fb reference. table 4. static electrical characteristics (continued) characteristics noted under conditions 2.7 v d v in d 5.5 v, - 20 q c d t a d 85 q c, gnd = 0 v, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 12 freescale semiconductor 34704 electrical characteristics static electrical characteristics pvin5 leakage current (off state) @25c i pvin5_lkg - - 1.0 p a sw5d leakage current (off state) @25c i sw5d_lkg - - 1.0 p a sw5u leakage current (off state) @25c i sw5u_lkg - - 1.0 p a regulator 6 (16) output voltage range v out 5.0 15 15 v output accuracy - -4.0 - 4.0 % line/load regulation (15) reg ln/ld -1.0 - 1.0 % feedback reference voltage v fb - 0.600 (17) - v dynamic voltage scaling range v dyn -10 - 10 % dynamic voltage scaling step size v dyn_step - 2.5 - % continuous output current (15) i out - 50 60 ma over-current limit (detected in low side fet) i lim_ion - 3.0 - a short-circuit current limit (detected in the blocking fet) i short_ion - 4.5 - a over-current limit accuracy - -20 - 20 % n-ch switch power mosfet r ds(on) r ds(on) - sw - 200 - m : n-ch synch. power mosfet r ds(on) r ds(on) - sy - 600 - m : n-ch shutdown power mosfet r ds(on) r ds(on) - sh - 200 - m : discharge mosfet r ds(on) r ds(on) - dis - 70 - : thermal shutdown threshold (15) t sd - 170 - c thermal shutdown hysteresis (15) t sd-hys - 25 - c sw6 leakage current (off state) @25c i sw6_lkg - - 1.0 p a regulator 7 (16) output voltage range v out -5.0 -7.0 -9.0 v output accuracy - -2.0 - 2.0 % line/load regulation (15) reg ln/ld -1.0 - 1.0 % feedback reference voltage v fb - 0.600 (17) - v continuous output current (15) i out - 50 60 ma discharge mosfet r ds(on) r ds(on) - dis - 55 - : gate drive voltage high level (@ -50 ma, v in =3.6v) v in -v oh - 0.8 1.4 v gate drive voltage low level (@ 50 ma, v in =3.6v) v ol - 1.1 1.8 v vref7 output voltage v ref7 - 1.5 - v vref7 voltage accuracy - 1.43 - 1.57 v vref7 output load regulation (10 p a to 1.0 ma) reg ld 1.43 - 1.57 v notes 15. guaranteed by design 16. available only on the 34704a 17. v fb is 0.6v when the part ist powered up and no d vs is changed. dvs is ac hieved by modifying v fb reference. table 4. static electrical characteristics (continued) characteristics noted under conditions 2.7 v d v in d 5.5 v, - 20 q c d t a d 85 q c, gnd = 0 v, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 13 34704 electrical characteristics static electrical characteristics regulator 8 output voltage range v out 5.0 (19) 15 15 v output accuracy - -4.0 - 4.0 % feedback reference voltage v fb - 0.600 (20) - v feedback reference voltage on current regulation mode v fb - 0.230 (21) - v dynamic voltage scaling range v dyn -10 - 10 % dynamic voltage scaling step size v dyn_step - 2.5 - % line/load regulation (18) reg ln/ld -1.0 - 1.0 % continuous output current (18) i out - 15 30 ma over-current limit (detected in low side fet) i lim_ion - 1.0 - a short-circuit current limit (detected in the blocking fet) i short_ion - 1.5 - a over-current limit accuracy - -20 - 20 % n-ch switch power mosfet r ds(on) r ds(on) - sw - 450 - m : n-ch synch. power mosfet r ds(on) r ds(on) - sy - 1000 - m : n-ch shutdown power mosfet r ds(on) r ds(on) - sh - 450 - m : discharge mosfet r ds(on) r ds(on) - dis - 70 - : thermal shutdown threshold (18) t sd - 170 - c thermal shutdown hysteresis (18) t sd-hys - 25 - c sw8 leakage current (off state) @25c i sw8_lkg - - 1.0 p a notes 18. guaranteed by design 19. when battery voltage is higher than 5.0v and vout8 is 5.0v, a pol arization diode is necessary to achieve accurate output vol tage. see component calculation on page 39 for further details. 20. v fb is 0.6v when the part ist powered up and no d vs is changed. dvs is ac hieved by modifying v fb reference. 21. when in current regulation mode, the voltage reference is set to 0.230mv to set the maximum current, and it is internally de creased to achieve a factor of the maximum curr ent passing through the led string table 4. static electrical characteristics (continued) characteristics noted under conditions 2.7 v d v in d 5.5 v, - 20 q c d t a d 85 q c, gnd = 0 v, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 14 freescale semiconductor 34704 electrical characteristics dynamic electrical characteristics dynamic electrical characteristics table 5. dynamic electri cal characteristics characteristics noted under conditions 2.7v d v in d 5.5v, -20 q c d t a d 85 q c, gnd = 0v, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit i 2 c communication device physical addr ess (7 bit address) - $54 - maximum i 2 c speed - - 400 khz freq selectable switching frequency 1 f sw1 750 - 2000 khz selectable switching frequency 2 f sw2 250 - 1000 khz selectable switching frequency step size f step - 250 - khz switching frequency accuracy -10 - 10 % retry timeout period (23) t timeout - 10 - ms current limit monitoring over-current limit timer (23) t limit - 10 - ms retry timeout period (23) t retry - 10 - ms output over-voltage/under-voltage monitoring under-voltage threshold (response a) v uv-r - -20 - % over-voltage threshold (response a) v ov-r - 20 - % under-voltage threshold (response b) v uv-r - -20 - % over-voltage threshold (response b) v ov-r - 20 - % filter delay timer (23) t filter - 20 - p s rst rst reset delay (23) t rst-delay - 10 ms regulator 1 & vg operating frequency (22) , (23) f sw1 750 - 1500 khz operating frequency selection step size f step - 250 - khz constant time off value (23) t off - 1.0 - p s low side timeout (23) t timeout - 15 - p s regulator 2 operating frequency (23) f sw1 750 - 2000 khz operating frequency selection step size f step - 250 - khz notes 22. when reg1 is used, the maximum f sw1 frequency programed with external components should be 1500 khz 23. guaranteed by design.
analog integrated circuit device data freescale semiconductor 15 34704 electrical characteristics dynamic electrical characteristics regulator 3 operating frequency f sw1 750 - 2000 khz operating frequency selection step size f step - 250 - khz regulator 4 operating frequency f sw1 750 - 2000 khz operating frequency selection step size f step - 250 - khz regulator 5 operating frequency f sw1 750 - 2000 khz operating frequency selection step size f step - 250 - khz regulator 6 operating frequency f sw2 250 - 1000 khz operating frequency selection step size f step - 250 - khz regulator 7 operating frequency selections f sw2 250 - 1000 khz operating frequency selection step size f step - 250 - khz regulator 8 operating frequency f sw2 250 - 1000 khz operating frequency selection step size f step - 250 - khz table 5. dynamic elec trical characteristics characteristics noted under conditions 2.7v d v in d 5.5v, -20 q c d t a d 85 q c, gnd = 0v, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 16 freescale semiconductor 34704 functional description introduction functional description introduction the 34704 is an multi-channel power management ic (pmic) meant to address power management needs for various multimedia applications microprocessors in various configurations with a target overall efficiency of > 80% at typical loads. the 34704 accepts an input voltage from various sources: ?1 cell li-ion/polymer (2.7 to 4.2 v) ?5.0 v usb supply or ac wall adapter the different channels are: regulator regulator type v out typ (v) i out typ (ma) i out max (ma) target application reg1 (25) synchronous boost 5.0 100 500 +5.0 v ref reg2 synchronous buck-boost 2.8 / 3.3 200 500 p i/o reg3 synchronous buck 1.2 / 1.5 / 1.8 150 550 p core reg4 synchronous buck-boost 1.8 / 2.5 100 300 ddr reg5 synchronous buck-boost 3.3 150 500 p i/o reg6 (25) synchronous boost 15.0 20 60 ref+ reg7 (25) inverter boost -7.0 20 60 ref - reg8 synchronous boost 15.0 15 30 backlight display notes 24. synchronous buck-boost: these regulators c an work as pure buck regulator when the output voltage is lower than the input vol tage; and work as pure boost regulator when the input voltage is lo wer than the output voltage. compensation should be done for the w orst case scenario, which is in most of the cases when the device is working as a boost converter, after compensating for this scena rio it is recommended to verify the buck operation to assure stability in the whole operating range. 25. available only on the 34704a reg1, reg3, reg6, and reg8 use internal compensation, while reg2, reg4, reg5, and reg7 use external compensation. the switching frequency of all regulators except reg6, 7, & 8 can be selected through the freq pin between 750 khz and 2.0 mhz in 250 khz steps. the high frequency operation is me ant to minimize the size of external components while lower operating frequencies will allow for higher efficiency. reg7 is limited to operate at a lower frequency to minimize switching noise induced by driving the external switching mosfet, but also can operate at the 1.0 mhz value with prop er board layout. reg 6, 7, and 8 switching frequency can be selected between 250 khz and 1.0 mhz in 250 khz steps th rough i 2 c. for all regulators and at lower loads, a pulse skipping mode is imple mented to maintain high efficiency. note that pulse skipping occurs when the regulator enters into discontinuous conduction mode (dcm) at very light loads, however transitions between dcm and ccm may result in noisy switching node s, therefore it is recommended to design the regulators to work in ccm all the time. pulse skipping function is not guaranteed by circuit implementation. the 34704 uses 4 different p hases of switching for all regulators except reg6, 7, and 8, to spread out the current draw by the individual converters from the input supply over time, to reduce the peak input current demand. this allows for better emi performance and reduction in the input filter requirements. each regulator except reg1 uses an external feedback resistor divider to set the ou tput voltage. a ll output voltages can be adjusted dynamically (dynamic voltage scaling) on the fly through an i2c serial inte rface. all converters, except reg1, utilize automatic soft-sta rt by ramping the reference voltage to the error amplifier to prevent sudden change in duty cycle and output current/voltage at power up. reg1 (vg) will limit the inrush current by implementing a peak current detect and a constant off time. the 34704 is equipped with a dual function power on/off pi n ( onoff ). this pin can be controlled by a mechanical switch to turn the device on or off. pressing and releasing the mechanical switch turns the 34704 on while pressing and holding the switch for a time period (programmable through i 2 c) turns the 34704 off. enable/disable control is also granted through i 2 c for groups of regulators and the whole ic.
analog integrated circuit device data freescale semiconductor 17 34704 functional description functional pin description functional pin description reg5 boost stage bootstrap capacitor input pin (bt5u) connect a 1.0 p f capacitor between this pin and sw5u pin to enhance the gate of the switch power mosfet. reg4 buck stage bo otstrap capacitor input pin (bt4d) connect a 0.01 p f capacitor between this pin and sw4d pin to enhance the gate of the switch power mosfet. reg4 power supply input voltage (pvin4) this is the connection to the drain of the high side switch fet. input decoupling /filtering is required for proper reg4 operation. reg4 buck stage switching node (sw4d) the inductor is connected between this pin and the sw4u pin. reg4 regulated output voltage pin (vout4) connect this pin to the load and to the output filter as close to the pin as possible. reg4 boost stage switching node (sw4u) the inductor is connected between this pin and the sw4d pin. reg4 boost stage bootstrap capacitor input pin (bt4u) connect a 0.01 p f capacitor between this pin and sw4u pin to enhance the gate of the switch power mosfet. reg4 voltage feedback input for voltage regulation/programming (fb4) connect the feedback resistor divider to this pin. reg4 compensation network connection (comp4) reg4 compensation network connection. reg3 bootstrap capacitor input pin (bt3) connect a 0.01 p f capacitor between this pin and sw3 pin to enhance the gate of the switch power mosfet. reg3 power supply input voltage (pvin3) this is the connection to the drain of the high side switch fet. input decoupling /filtering is required for proper reg3 operation. reg3 switching node (sw3) the inductor is connected between this pin and the regulated reg3 output. reg3 output voltage return pin (vout3) this is the discharge path of reg3 output voltage. reg3 voltage feedback input for voltage regulation/programming (fb3) connect the feedback resistor divider to this pin. soft start time (ss) the soft start time for all regulators can be adjusted by connecting this pin to an external resistor divider between vddi and agnd pins. oscillator frequency (freq) the oscillator frequency can be adjusted by connecting this pin to an external resistor divider between vddi and agnd pins. this pin sets f sw1 value. reg8 voltage feedback input for voltage regulation/programming (fb8) connect the feedback resistor divider to this pin, when voltage mode control is used. when current mode control is used, connect this pin between the led string and an i set resistor to gnd to force the operating current. refer to figure 10 and figure 11 . exclude the components not used. reg8 bootstrap capacitor input pin (bt8) connect a 0.01 p f capacitor between this pin and sw8 pin to enhance the gate of the synchronous power mosfet. reg8 regulated output voltage pin (vout8) connect this pin directly to the load directly and to the output filter as close to the pin as possible. reg8 switching node (sw8) the inductor is connected bet ween this pin and vin pin. reg1 switching node (sw1) the inductor is connected bet ween this pin and vin pin. reg1 regulated output voltage before the cut-off switch (vg) reg1 regulated output voltage before the cutoff switch. this supplies the internal circuits and the gate drive.
analog integrated circuit device data 18 freescale semiconductor 34704 functional description functional pin description reg1 regulated output voltage pin (vout1) (34704a only) connect this pin directly to the load directly and to the output filter as close to the pin as possible. reg1 bootstrap capacitor input pin (bt1) connect a 1.0 p f capacitor between this pin and sw1 pin to enhance the gate of the switch power mosfet. i 2 c serial interface clock input (scl) i 2 c serial interface clock input. i 2 c serial interface data input (sda) i 2 c serial interface data input power reset output signal (microprocesso r reset) ( rst ) this is an open drain output and must be pulled up by an external resistor to a supply voltage like v in . reg7 compensation network connection (comp7) reg7 compensation network connection. reg7 resistor feedback network reference voltage (vref7) (34704a only) connect this pin to the bottom of the feedback resistor divider. reg7 voltage feedback input for voltage regulation/programming (fb7) (34704a only) connect the feedback resistor divider to this pin. reg7 external power mosfet gate drive (drv7) (34704a only) reg7 external power mosfet gate drive. reg7 output voltage return pin (vout7) (34704a only) this is the discharge path of reg7 output voltage. reg6 voltage feedback input for voltage regulation/programming (fb6) (34704a only) connect the feedback resistor divider to this pin. reg6 bootstrap capacitor input pin (bt6) (34704a only) connect a 0.01 p f capacitor between this pin and sw6 pin to enhance the gate of the synchronous power mosfet. reg6 switching node (sw6) (34704a only) the inductor is connected bet ween this pin and the vin pin. reg6 regulated output voltage pin (vout6) (34704a only) connect this pin directly to the load directly and to the output filter as close to the pin as possible. analog ground (agnd) analog ground of the ic. battery voltage connection (vin) input decoupling /filtering is required for the device to operate properly. internal supply voltage (vddi) connect a 1.0 p f low esr decoupling filter capacitor between this pin and gnd. battery detection (lion) pull this pin high to vin to indicate a connection to a li-ion battery. dual function ic turn on/off ( onoff ) this is a hardware enable/dis able for the 34704. it can be connected to a mechanical switch to turn the power on or off. reg2 boost stage bootstrap capacitor input pin (bt2u) connect a 1.0 p f capacitor between this pin and sw2u pin to enhance the gate of the switch power mosfet. reg2 compensation network connection (comp2) reg2 compensation network connection. reg2 voltage feedback input for voltage regulation/programming (fb2) connect the feedback resistor divider to this pin. reg2 buck stage bootstrap capacitor input pin (bt2d) connect a 1.0 p f capacitor between this pin and sw2d pin to enhance the gate of the switch power mosfet. reg2 power supply input voltage (pvin2) this is the connection to the drain of the high side switch fet. input decoupling /filtering is required for proper reg2 operation.
analog integrated circuit device data freescale semiconductor 19 34704 functional description functional pin description reg2 buck stage switching node (sw2d) the inductor is connected between this pin and the sw2u pin. reg2 regulated output voltage pin (vout2) connect this pin to the load and to the output filter as close to the pin as possible. reg2 boost stage switching node (sw2u) the inductor is connected between this pin and the sw2d pin. reg5 boost stage switching node (sw5u) the inductor is connected between this pin and the sw5d pin. reg5 regulated output voltage pin (vout5) connect this pin to the load and to the output filter as close to the pin as possible. reg5 buck stage switching node (sw5d) the inductor is connected between this pin and the sw5u pin. reg5 power supply input voltage (pvin5) this is the connection to the drain of the high side switch fet. input decoupling /filtering is required for proper reg5 operation. reg5 buck stage bootstrap capacitor input pin (bt5d) connect a 1.0 p f capacitor between this pin and sw5d pin to enhance the gate of the switch power mosfet. reg5 voltage feedback input for voltage regulation/programming (fb5) connect the feedback resistor divider to this pin. reg5 compensation network connection (comp5) reg5 compensation network connection. power ground connection for all of the regulators except reg7 (pgnd) power ground connection for all of the regulators except reg7.
analog integrated circuit device data 20 freescale semiconductor 34704 functional description functional internal block description functional internal block description * figure 4. mc34704 functional internal block diagram internal bias circuit gate driver voltage (vg) reg1/vg is the main regulator of the 34704 ic and will be used to supply internal circuitry and voltage biases through the vg output. it also provides the gate drive voltage for the rest of the regulators and itself. see power-up sequence on page 28 for more details on how reg1 is a critical part of powering up the 34704. based on this, reg1 will need extra circuitry to help it boot up until its output voltage is high enou gh that it can supply internal circuitry for the main control loop to take over. reg1 vg starts up in peak current detect pfm mode and reg1 vg output starts rising. when the appropriate internal circuitry is alive and the switching frequency f sw1 is selected, the pwm control of reg1 can take over. vref generator - in ternal reference each one of the regulators in the 34704 uses a dac which is co ntrolled by the i 2 c interface to generate a dynamic vref voltage for setting the output voltage on each regulator. vddi reference voltage the 34704 uses the internal vg voltage to provide a preci se low current 2.5 v voltage that is meant to serve as referen ce voltage to derive the freq and ss voltage needed to set the switching frequency 1 (fsw1) and the soft start, respectively. fault detection and protection thermal limit detection there is a thermal sensor for each regulator except reg7. all regu lators of the corresponding group will shutdown if at least one of them reaches the t hermal limit. if either reg2, reg3 or reg4 reaches its thermal limit, the whole part will shutdown immediately. over-current & shor t circuit monitoring the current limit circuitry has two levels of current limiting: ? a soft over-current limit (o ver-current limit): if the peak current reaches the typical over-current limit, the switcher will start a cycle-by-cycle oper ation to limit the current and a 10 ms current limit timer starts. the switcher will stay in this mo de of operation until the part regains normal
analog integrated circuit device data freescale semiconductor 21 34704 functional description functional internal block description operation, or shuts down after a failure to regain normal operation. ? a hard over-current limit (short -circuit limit) that is higher than the cycle by cycle limit at which the device reacts by shutting down the output immediately. this is necessary to prevent damage in case of a sh ort-circuit. after that, only grpb will attempt a one time re try after a time-out period of 10 ms and will go through a new soft start cycle output over-voltage/und er-voltage monitoring in the case of an output over-voltage/under-voltage, the user has two options that can be programmed through the i 2 c interface: response a: the output will switch off automatically and the 34704 would alert the processor through i 2 c that such an event happened. response b: the output will no t switch off. rather the 34704 communicates to the processor that an over-voltage/ under-voltage condition has occurred and waits for the processor decision to either shutoff or not; in the mean time the control loop will try to fix itself. note: if response a is set on any of the regulators from grpb, and a ov/uv event occurs in the correspondig regulator, the complete device will shutdown and try to restart as long as the ov/uv is no longer present. this will also set the rst signal low until reg2, 3 and 4 are on regulation. logic and control startup sequencing at power up, the vg regulator starts ramping up in peak detect mode. meanwhile, vddi is tracking vg until it reaches regulation and releases a por signal that enables the internal circuitry and reads the freq and ss configuration to ramp up reg2, reg3 and reg4, that serve as the mpu main power supplies. once the mpu is up, i 2 c communication is available to enable or disable grpa, grpc, grpd and grpe. an extra sequence can be configured for reg5, reg6 and reg7, changing the order in which they ramp up when enabled. see power-up sequence on page 28 . soft start control during power up the 34704 reads the ss terminal to configure a default soft start timing for all regulators when these are enabled. soft start for reg5 to reg8 can be changed via i 2 c at any time after po wer up has successfully completed. phase control reg1 to reg5 use the main switching frequency fsw1, which is configured through t he freq terminal at power up. fsw1 uses 4 different phases of switching (clock is 80 degrees out of phase) to spre ad out the current draw by the individual converters from the input supply over time to reduce the peak input current demand. the remaining regulators use fsw2 which can be programmed at any time via i 2 c after a successful power up sequence. fault register the 34704 has a dedicate fault register accessible via i 2 c which indicate which regulator is detecting a fault situation. in addition to this, each channel has its own fault register which indicates the type of fault detected in t hat regulator. i 2 c communication and registers the 34704 can communicate using a standard i 2 c, communication protocol or an accurate i 2 c protocol. during the first one, the device proc esses the given command as soon as it has received it. during the accurate data communication, the device requ ires that each read/write command be sent twice to validate the data. the 34704 provides a user accessible register map that allows various general ic configurations as well as independent control of each regulator, including fault flag registers and all configurable features for each regulator. output groups - regulators the 34704 is divided in 5 different groups which are arranged as follows: ? grpa: includes reg1 (26) (vout1) ? grpb: includes reg2, reg3, and reg4 ? grpc: includes reg5, reg6 (26) , and reg7 (26) ? grpd: includes reg8 ? grpe: this is a special group. it includes reg5 when grpc/e power sequencing option#1 is chosen turning on/off each group would cause all contained regulators to turn on/off. notes 26. only on 34704a
analog integrated circuit device data 22 freescale semiconductor 34704 functional description functional internal block description regualator overview with efficiency analysis reg1 (34704a only) reg1 is a synchronous boost pwm voltage-mode control dc/dc regulator available only in the 34704a. even though reg1 is a synchronous regulator, it is recommended to have a diode connected externally across its synchronous mosfet. when the battery volt age is above reg1?s output (>5.0 v) as the case might be when connected to the usb supply or wall adaptor, the reg1 power mosfets will be tri- stated and the voltage on the output will be battery minus the diode drop. this will help maintain reg1?s output to a maximum of 5.2 v and not allow it to drift all the way to 5.5 v. the switcher will operate in dcm at very light loads to allow pulse skipping. on the 34704a, when the appropriate command is received from the processor to turn on vout1, then the isolation fet of reg1 would turn on gradually to avoid any inrush current out of vg and to ramp the vout1 voltage in a controlled manner. reg1 vout1 will be discharged every time grpa is shutting down and it will be held low by the discharge fet as long as possible. characteristics ? it powers up directly from the battery ? operates at a switching frequency equals to f sw1 ? drives integrated low r ds(on) n-channel power mosfets (nhv_hc) as its output stage ? it offers load disconnect from the input battery when the output is off (true cutoff) ? the output is 4% accuracy ? output voltage is set to 5.0 v by means of an internal resistor divider ? the output can be adjusted up or down at 2.5% for a total of 10% on each direction allowing dynamic voltage scaling ? uses a bootstrap network with an internal diode to power its synchronous mosfet ? all gate drive circuits are s upplied from reg1?s own vg output. ? uses integrated compensation ? the output is monitored for under-voltage and over- voltage conditions ? the output is monitored for over-current and short-circuit conditions ? the regulator is monitored for over-temperature conditions operation modes the vg output is always active as long as: ? the ic is not in an under-voltage lockout and ? no shutdown signal through the onoff pin is present and ? there is no alloff shutdown command through the i 2 c interface and ? no faults exist that would cause the 34704 to shutdown the vout1 output will be active when: ? vg output is available and ? there is no grpa shutdown command through the i 2 c interface and ? no faults exist that would cause the vout1 to shut down reg2 this is a 4-switch synchro nous buck-boost pwm voltage- mode control dc/dc regulator. see power-up sequence on page 28 for more details on when reg2 is powered up in the sequence. the switcher will operate in dcm at very light loads to allow pulse skipping. vout2 will be discharged every time the regulator is shutting down and it will be held low by the discharge fet as long as possible. characteristics ? it powers up directly from the battery ? operates at a switching frequency equals to f sw1 ? drives integrated low r ds(on) n-channel power mosfets (nhv_hc) as its output stage ? the output is 2% accuracy ? output voltage is adjustable by means of an external resistor divider ? the output can be adjusted up or down at 2.5% steps for a total of +17.5% to -20.0% on each direction allowing dynamic voltage scaling ? uses bootstrap networks with an internal diode to power its high side mosfets ? all gate drive circuits are supplied from vg ? uses external compensation ? the output is monitored for under-voltage and over- voltage conditions ? the output is monitored for over-current and short-circuit conditions ? the regulator is monitored for over-temperature conditions operation modes the switcher will be active when: ? vg is in regulation and ? there is no grpb shutdown command through the i 2 c interface and ? no faults exist that would cause grpb to shut down reg3 this is a synchronous buck pwm voltage-mode control dc/dc regulator.
analog integrated circuit device data freescale semiconductor 23 34704 functional description functional internal block description see power-up sequence on page 28 for more details on when reg3 is powered up in the sequence. the switcher will operate in dcm at very light loads to allow pulse skipping. vout3 will be discharged every time the regulator is shutting down and it will be held low by the discharge fet as long as possible. characteristics ? it powers up directly from the battery ? operates at a switching frequency equals to f sw1 ? drives integrated low r ds(on) n-channel power mosfets (nhv_hc) as its output stage ? the output is 4% accuracy ? output voltage is adjustable by means of an external resistor divider ? the output can be adjusted up or down at 2.5% steps to achieve from +17.5% to -20.0% on each direction allowing dynamic voltage scaling using the i 2 c dvs register. ? an extra fine voltage scaling in 0.5% steps helps to adjust down the output voltage as low as 40%. ? uses a bootstrap network with an internal diode to power its switch mosfet ? all gate drive circuits are supplied from vg. ? uses integrated compensation. ? the output is monitored for under-voltage and over- voltage conditions ? the output is monitored for over-current and short-circuit conditions ? the regulator is monitored for over-temperature conditions operation modes the switcher will be active when: ? vg is in regulation and ? there is no grpb shutdown command through the i 2 c interface and ? no faults exist that woul d cause grpb to shut down reg4 this is a 4-switch synchronous buck-boost pwm voltage- mode control dc/dc regulator. see power-up sequence on page 28 for more details on when reg4 is powered up in the sequence. the switcher will operate in dcm at very light loads to allow pulse skipping. vout4 will be discharged every time the regulator is shutting down and it will be held low by the discharge fet as long as possible. characteristics ? it powers up directly from the battery ? operates at a switching frequency equals to f sw1 ? drives integrated low r ds(on) n-channel power mosfets (nhv_hc) as its output stage ? the output is 2% accuracy ? output voltage is adjustable by means of an external resistor divider ? the output can be adjusted up or down at 2.5% steps for a total of +17.5% to -20.0% on each direction allowing dynamic voltage scaling. ? uses bootstrap networks with an internal diode to power its high side mosfets ? all gate drive circuits are supplied from vg. ? uses external compensation ? the output is monitored for under-voltage and over- voltage conditions ? the output is monitored for over-current and short-circuit conditions ? the regulator is monitored for over-temperature conditions operation modes the switcher will be active when: ? vg is in regulation and ? there is no grpb shutdown command through the i 2 c interface and ? no faults exist that would cause grpb to shut down reg5 this is a 4-switch synchro nous buck-boost pwm voltage- mode control dc/dc regulator. see power-up sequence on page 28 on for more details on when reg5 is powered up in the sequence. the switcher will operate in dcm at very light loads to allow pulse skipping. vout5 will be discharged every time the regulator is shutting down and it will be held low by the discharge fet as long as possible. characteristics ? it powers up directly from the battery ? operates at a switching frequency equals to f sw1 ? drives integrated low r ds(on) n-channel power mosfets (nhv_hc) as its output stage ? the output is 2% accuracy ? output voltage is adjustable by means of an external resistor divider ? the output can be adjusted up or down at 2.5% steps for a total of +17.5% to -20.0% on each direction allowing dynamic voltage scaling. ? uses bootstrap networks with an internal diodes to power its high side mosfets ? all gate drive circuits are supplied from vg. ? uses external compensation ? the output is monitored for under-voltage and over- voltage conditions
analog integrated circuit device data 24 freescale semiconductor 34704 functional description functional internal block description ? the output is monitored for over-current and short-circuit conditions ? the regulator is monitored for over-temperature conditions operation modes the switcher will be active when: ? vg is in regulation and ? there is no grpc (or grpe) shutdown command through the i 2 c interface and ? no faults exist that would ca use grpc (or grpe) to shut down reg6 (only 34704a) this is a synchronous boost pwm voltage-mode control dc/dc regulator. see power-up sequence on page 28 for more details on when reg6 is powered up in the sequence. the switcher will operate in dcm at very light loads to allow pulse skipping. vout6 will be discharged every time the regulator is shutting down and it will be held low by the discharge fet as long as possible. characteristics ? it powers up directly from the battery ? operates at a switching frequency equals to f sw2 ? drives integrated low r ds(on) n-channel power mosfets (nvhv_lc) as its output stage ? it offers load disconnect from the input battery when the output is off (true cut-off) ? the output is 4% accuracy ? output voltage is adjustable by means of an internal resistor divider ? the output can be adjusted up or down at 2.5% steps for a total of 10% on each direction allowing dynamic voltage scaling ? uses a bootstrap network with an internal diode to power its synchronous mosfet ? all gate drive circuits are supplied from vg. ? uses integrated compensation. ? the output is monitored for under-voltage and over- voltage conditions ? the output is monitored for over-current and short-circuit conditions ? the regulator is monitored for over-temperature conditions operation modes the switcher will be active when: ? vg is in regulation and ? there is no grpc shutdown command through the i 2 c interface and ? no faults exist that woul d cause grpc to shut down reg7 (only 34704a) this is a none-synchronous buck-boost inverting pwm voltage-mode control dc/dc regulator. see power-up sequence on page 28 for more details on when reg7 is powered up in the sequence. the switcher will operate in dcm at very light loads to allow pulse skipping. vout7 will be discharged every time the regulator is shutting down and it will be held high to ground by the discharge fet as long as possible. characteristics ? it powers up directly from the battery ? operates at a switching frequency equals to f sw2 ? drives an external p-channel power mosfet ? the output is 2% accuracy ? output voltage is adjustable by means of an external resistor divider ? the output can be adjusted up or down at 2.5% steps for a total of 10% on each direction allowing dynamic voltage scaling. ? all gate drive circuits are supplied from v g ? uses external compensation, the type is up to the designer ? the output is monitored for under-voltage and over- voltage conditions operation modes the switcher will be active when: ? vg is in regulation and ? there is no grpc shutdown command through the i 2 c interface and ? no faults exist that would cause grpc to shut down reg8 this is a synchronous boost pwm voltage-mode control dc/dc regulator. see power-up sequence on page 28 for more details on when reg8 is powered up in the sequence. vout8 will be discharged every time the regulator is shutting down and it will be held to ground by the discharge fet as long as possible. this regulator offers either voltage regulation for organic leds or current regulation for lcd backlighting leds. it provides either voltage or current feedback for these purposes through the same feedback pin. the regulator cannot drive only 1led with a forward voltage drop of less than the battery input voltage. the processor would set the reg8 register through i 2 c before enabling reg8 to indicate if voltage regulation or current regulation will be used. characteristics ? it powers up directly from the battery
analog integrated circuit device data freescale semiconductor 25 34704 functional description functional internal block description ? operates at a switching frequency equals to f sw2 ? drives integrated low r ds(on) n-channel power mosfets (nvhv_lc) as its output stage ? it offers load disconnect from th e input battery when the output is off (true cut-off) ? the output is 4% accuracy ? output voltage is adjustable by means of an external resistor divider when in voltage regulation mode ? a 240 mv current limit comparator wil l be used to program/ sense the voltage drop across th e current setting resistor at the bottom of the led string connected to the reg8 output when the current regulation mode is selected . this will be used to program the maximum current flowing and will regulate it ? the output can be adjusted up or dow n at 2.5% steps for a total of 10% on each direction allowing dynamic voltage scaling ? maximum output current is ad justable by means of an external resistor connected to the fb8 pin and then the output current can be scaled down from the set maximum in 16 steps through i 2 c interface ? uses a bootstrap network with an internal diode to power its synchr onous mosfet ? all gate drive circuits are supplied from vg. ? uses integrated compensation ? the output is monitored for over-current and short-circuit cond itions ? the regulator is monitored for over-temperature conditions ? the output is monitored for under-voltage and over- voltage conditions operation modes the switchers will be active when: ? vg is in regulation and ? there is no grpd shutdown command through the i 2 c interface and ? no faults exist that woul d ca use grpd to shut down overall efficiency analysis in battery applications, it is highly recommended to power every single regulator directly from the battery to obtain full output capability: vbat v1 (5.0 v) reg1 vbat v2 (2.8 / 3.3 v) reg2 vbat v3 (1.2 v / 1.5 v / 1.8 v) reg3 vbat v4 (1.8 v / 2.5 v) reg4 vbat v5 (3.3 v) reg5 vbat v6 (15 v) reg6 vbat v7 (-7.0 v) reg7 vbat v8 (15 v) reg8 figure 5. overall efficiency analysis efficiency analysis includes the following losses: ? mosfet conduction losses ? mosfet switching losses (e xce pt for reg7 due to external mosfet and board layout dependence) ? mosfet gate charging losses ? mosfet deadtime losses ? external diode losses (only for reg7) ? inductor winding dc losses ? inductor core losses (assumed to be 20% of dc losses as a rule of th umb) ? output ac losses efficiency analysis in this configuration, all of the regu lators are supplied or powered directly with 3.6 v nominal, battery voltage. efficiency was calculated using the maximum allowed fre quency of 1.5 mhz and 1.0 mhz for f sw1 and f sw2 , respectively, in this configuration. as a result, the following numbers are valid for worst case operation conditions. the following table shows the detailed analysis for each regu lator with v2 at 3.3 v, v3 at 1.2 v, and v4 at 1.8 v.
table 6. regulator analysis table reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 vin (v) 3.60 3.60 3.60 3.60 3.60 3.60 3.60 3.60 vout (v) 5.00 3.30 1.20 1.80 3.30 15 -7 15 iout_typ (a) 0.100 0.200 0.150 0.100 0.150 0.050 0.050 0.015 iout_max (a) 0.500 0.500 0.550 0.300 0.500 0.060 0.060 0.030 dcr(m ) 230 230 230 310 230 230 230 230 cout ( f) 22 22 22 22 22 22 22 22 esr (m ) 9.00 9.00 9.00 9.00 9.00 9.00 9.00 9.00 fsw (khz) 1500 1500 1500 1500 1500 1000 1000 1000 lout ( h) 1.50 1.50 1.50 1.50 1.50 4.70 4.70 4.70 iin_typ (a) 0.154 0.201 0.063 0.059 0.150 0.254 0.107 0.077 iin_max (a) 0.540 0.502 0.209 0.178 0.501 0.304 0.128 0.154 ilout_peak (a) 0.724 0.510 0.649 0.444 0.512 0.444 0.443 0.297 icout_rms (a) 0.212 0.005 0.074 0.076 0.0006 0.071 0.129 0.043 pout (w) 0.500 0.660 0.180 0.180 0.495 0.750 0.350 0.225 ploss on chip (w) 0.042 0.047 0.038 0.028 0.034 0.135 0.000 0.045 ploss total (w) 0.044 0.049 0.041 0.030 0.035 0.145 0.027 0.047 pin (w) 0.544 0.709 0.221 0.210 0.530 0.895 0.377 0.272 n (%) 91.90% 93.12% 81.48% 85.91% 93.33% 60.00% 69.00% 64.00% table 7. 34704a overall system efficiency 84% overall system pout (w) 3.340 ploss on chip (w) 0.369 ploss total (w) 0.41 pin (w) 3.75 n (%) 84.00% table 8. 34704b overall system efficiency 89% overall system pout (w) 1.74 ploss on chip (w) 0.192 ploss total (w) 0.202 pin (w) 1.942 n (%) 89.6% analog integrated circuit device data 26 freescale semiconductor 34704 functional description functional internal block description
analog integrated circuit device data freescale semiconductor 27 34704 functional description functional internal block description mc34704 efficiency waveforms reg1 efficiency 0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 0 100 200 300 400 500 600 iout reg2 efficiency 0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 0 100 200 300 400 500 600 iout reg3 efficiency 0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 0 100 200 300 400 500 600 iout reg4 efficiency 0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 0 50 100 150 200 250 300 350 iout reg5 efficiency 0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 0 100 200 300 400 500 600 iout reg6 efficiency 0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 0 10203040506070 iout reg7 efficiency 0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 0 10203040506070 iout reg8 efficiency 0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 0 5 10 15 20 25 30 35 iout
analog integrated circuit device data 28 freescale semiconductor 34704 functional device operation operational modes functional device operation operational modes power-up sequence following is the power up sequence from a battery connection or a power on signal through the onoff pin. 1. battery initially connected to vin. 2. lion pin is used to determine if a battery is being used (high for li-ion battery). 3. at initial power up from a cold start like the above with the battery first connected, the status of the onoff pin is ignored and 34704 moves forward to step (5). 4. after the cold start or battery insertion power up, activity on the onoff pin is used to determine if the device is enabled or disabled. if the device is disabled, then nothing happens. if the device is enabled then, 34704 moves forward to step (5). 5. the input battery uvlo signal de-asserts if the input voltage is above the uvlo rising threshold. 6. reg1 vg starts up in peak detect pfm and reg1 vg output starts rising. 7. v ddi output voltage will start tracking reg1 vg output. 8. when reg1 vg output rises high enough such that v ddi voltage is in regulation a por signal is released and all internal circuitry can be enabled. i 2 c communication will remain disabled for normal power up sequence. the values of the freq and ss pins are read at this point. 9. reg1 pwm control loop can take over control of reg1 output once the vg voltage reaches a certain threshold set internally. 10. when reg1 is in regulation, it will be used to supply the power mosfet gate voltage for all of the other regulators except reg7. 11. reg3 is enabled, then when reg3 is in regulation. 12. reg2 is enabled, then when reg2 is in regulation. 13. reg4 is enabled, then when reg4 is in regulation. 14. i 2 c communication is enabled now since the processor supplies are up. 15. 34704 will de-assert the rst signal to indicate a ?power good? after 10 ms of wait time. this output will be connected to the reset pin of the microprocessor. 16. the microprocessor then takes over and can enable reg1 vout1 and reg5 through reg8. the processor needs to send a command for reg8 mode of operation. the processo r can also change reg5-8 soft start time before enabling them. the processor can also power down the syst em with an alloff command. for power sequencing needs, the different regulators are grouped based on their function and how they relate to each other and the entire system. this makes power sequencing control a much easier task for the user where most of the group internal sequencing in now handled by the pmic. all the processor has to do is to command the group and not each regulator. the regulators groups are as follows: ? grpa: includes reg1 (vout1) ? grpb: includes reg2, reg3, and reg4 ? grpc: includes reg5, reg6, and reg7 ? grpd: includes reg8 ? grpe: this is a special group. it includes reg5 when grpc/e power sequencing option#1 is chosen shutdown sequences ? processor can disable vout1 (grpa) at any point it desires ? processor can disable reg8 (grp d) at any point it desires ? processor can disable reg5 (grp e) at any point it desires if sequencing option#1 is picked ? processor can shutdown grpc according to the power sequencing options 1, 2, 3, or 4 (see section ? i 2 c user interface ?) ? if any regulator in grpc is shutting down due to a fault, the other regulators in grpc will also shutdown by following the grpc power sequencing optio ns 1, 2, 3, or 4 (see section ? i 2 c user interface ?) ? if any regulator in grpb is shutting down due to a fault, the other regulators in grpb will also shutdown by following the processor supplies shutdown sequence. then, grpa, grpc, grpd, and grpe (if applicable) will simultaneously shutdown keeping any sequencing within each group as necessary. vg will stay alive to perform a power up retry for grpb but only for one time. if the power up cycle is successful, then normal operation is back. if the fault returns, then the shutdown sequence is repeated and then vg shuts down ? processor can shutdown the 34704 by sending an ?alloff? command, then grpa, grpc, grpd, and grpe (if applicable) will simultaneously shutdown keeping any sequencing within each group as necessary. then, grpb will shutdown according to the processor supply shutdown sequence. then, vg will shut down. ? the previous shutdown event can also happen through the onoff pin by pressing and holding the pin for a time period (programmable through i 2 c with a default of 1sec) ? during battery depletion and when the input voltage passes the uvlo falling threshold, all of the outputs will be disabled without honouring the power down sequence this is to guarantee that the outputs are off and battery is not depleted further.
analog integrated circuit device data freescale semiconductor 29 34704 functional device operation operational modes ? in any of the previous shut down sequences, vg output will stay alive to maintain internal circuitry and logic until all other regulators are off, then it will shut off. power supply the battery voltage range is the following depending on the application: ? 1-cell li-ion/polymer: 2.7 to 4.2 v. typ value is 3.6 v ? usb supply or ac wall adapter: 4.5 to 5.5 v. typ value is 5.0 v. this gives a total input voltage supply range of 2.7 to 5.5 v for the regulators, each one will be supplied separately th rough its own power input. lion pin lion pin is always tied to vin level. frequency setting pin (freq pin) there are two switching freq uencies on board the 34704, one for reg6, 7 & 8, and the other for the rest of the regulators. to avoid any jitter or interference problems by having two oscillators on board, the switching frequency will be derived from the main oscillator using a frequency divider. the switching frequency will be selectable for all of the regu lators. reg6, 7 & 8 switching frequency (f sw2 ) will be selectable through i 2 c to be between 250 khz and 1.0 mhz in 250 khz steps. the rest of t he reg ulators switching frequency (f sw1 ) will be selectable through the freq pin and can be selected between 750 khz and 2.0 mhz, in 25 0 khz steps. f sw1 default value is 2.0 mhz. this value is obtained by tying the fr eq pin to vddi. f sw2 default value is 500 khz. f sw1 will be selectable through programming the freq pin with an external resistor divider connected between vddi and agnd pins. f sw2 will only be selectable through i 2 c. please refer to the ?i 2 c programmability? section. the 34704 uses 4 different phases of switching (clock is 80 degrees out of phase) for f sw1 to spread out the current draw by the individual converters from the input supply over time to reduce the peak input current demand. this allows for better emi performance and reduc tion in the input filter requirements. f sw1 has no phase relation with f sw2 . the following distribution is shown for f sw1 of 2.0 mhz. the regu lators grouping is based on their maximum current draw and attempts to reduce the effect on the input current draw. 500 ns 500 ns 500 ns 500 ns reg1/vg reg1/vg reg1/vg reg1/vg reg2 reg2 reg2 reg2 reg5, reg3 reg5, reg3 reg5, reg3 reg4 reg4 reg4 soft start pin (ss pin) initially at power up, the soft st art time will be set for all of the regulators through programming the ss pin with an external resistor divider con nected between vddi and agnd pins (see the 34704a typical application diagram ). after power up, the soft start value for reg5 through reg8 can be changed and programmed through i 2 c. reg2 through reg4 soft start value is only set by the ss pin and cannot be programmed through i 2 c. see section ?i 2 c programmability? for more details. onoff pin this is a hardware enable/disable feature or pin for the 34704 : ? it can be connected to a mechanical switch to turn the power on or off ? the device is power off by a command via the i 2 c interface as well ? the power off by hardware can be masked by a command via the i 2 c interface ? if the device is off and a falling edge is detected at the onoff pin, the device starts up ? if and only if the device is on and the onoff pin is pulled down for a time period (1s as a default and selectable to 2.0 sec, 1.5 sec, 1.0 sec or 0.5 sec via the i 2 c interface), then the device powers off after a second time period elapses unless it is masked by a command via the i 2 c interface: ? the second period is the same amount of time as the first pe riod so that the counter can be shared ? when the first period elapses a shutdown flag is set to al ert the processor that a shutdown signal has been activated. the onoff pin can be released after this flag is set without affecting what will happen next ? a cpu can read out the shutdown flag to determine what to do ? power off the device immediately by a command via i 2 c interface (alloff command) ? ignore the power off by sending a command via i 2 c interface to clear the shutdown flag
analog integrated circuit device data 30 freescale semiconductor 34704 functional device operation operational modes ? do nothing until the second time period expires and let the device power off by itself the onoff pin is edge sensitive and activates on a falling edge. it is normally pulled high. during this time, the processor can abort the shutdown process or shutdown immediat ely before the 2nd period elapses with an i 2 c command 1 st period 2 nd period programmable shutdown delay 1 st period programmable shutdown delay 2 st period shutdown flag asserted shutdown if no processor communication turn on on/off pin can be released during this period without affecting t he device response process 1 0 figure 6. hardware power up/down timing rst output signal pin this is a power reset output signal. it is an open drain output that should be connected to the reset input of the microprocessor. an external pull up resistor should be connected to this output and is recommended to be pulled up to v2 for best performance (if this pin is pulled up to the vin pin, then the 1.0 a shutdown current budget is not gua ranteed) at power up, the rst pin is asserted (low) to keep the processor in ?reset?. when vg, reg2, reg3, and reg4 are all in regulation (both ov and uv flags for each regulator are de-asserted) and no faults exist, the rst output is de- asserted after a 10 ms delay to take the processor out of reset. t hen the processor can go through its own internal power up sequence and can start communicating to the rest of the system. if any of the above four regul ators has a ny of the following faults: over-temperature, short-ci rcuit, over-current for more than 10 ms, over-voltage in response a, under-voltage in respon se a, or is shutting down normally, the rst output is asserted to put the processor ba ck in reset. if any of the above four regulators has an over-voltage response b fault or an under-voltage response b fault, the rst output will not be asserted (only the ov and uv flags will be available for the microprocessor to read). thermal limit detection there is a thermal sensor for each regulator except reg7. it uses an external mosfet. current limi t monitoring the current limit circuitry has two levels of current limiting: ? a soft over-current limit (ove r- current limit): if the peak current reaches the typical ove r-current limit, the switcher will start a cycle-by-cycle operat ion to limit the current and a 10 ms current limit timer starts. the switcher will stay in this mo de of operation until on e of the following occurs: ? the current is reduced back to the normal level inside the 10 ms timer and in this case normal operation is gained back ? the output reaches the thermal shutdown limit and turns off ? the current limit timer expires without gaining normal op eration at which point the output turns off. then only for grpb, at the end of a timeout period of 10 ms, the ou tput will attempt to restart again but for one time only. ? the output current keeps increasing until it reaches the secon d over-current limit, see below for more details ? a hard over-current limit (short circuit limit) that is higher than the cycle by cycle limit at which the device reacts by shutting down the output immediat ely. this is necessary to prevent damage in case of a short-circuit. after that, only grpb will attempt a one time retry after a timeout period of 10ms and will go throu gh a new soft start cycle output over-voltage/under-voltage monitoring in the case of an output over-voltage/under-voltage, the user has two options that can be programmed through the i 2 c interface: response a: the output will sw itch off automatically and the 34704 would alert the processor through i 2 c that such an event happened. response b: the output will not switch off. rather the 34 704 communicates to the processor that an over-voltage/ under-voltage condition has occurred and wait for the
analog integrated circuit device data freescale semiconductor 31 34704 functional device operation logic commands and registers processor decision to either shutoff or not, in the mean time the control loop will try to fix itself. to avoid erroneous conditions, a 20 s fil ter will be implemented. the ov/uv fault flag is masked during dvs until dvsstat fla g is asserted ?done?. to keep the rst output low during ramp up and until the soft start is done, the ov/uv protection is masked from reporting that the output is in regulation. logic commands and registers i 2 c user interface the 34704 communicates via i 2 c using a default device address $54 to access all user registers and program all regulators features independently. physical address is in a 7- bit format. the extra bit to complete the 8-bit indicates the reading or writing mode as shown in figure 7 and figure 8 . after each byte read or sent, the mc34704 answers with an acknowl edge bit, indicating the bite was transferred successfully. 0 ack 0xxxxxxx sub-address (msb=0) 0 xxxxxxxx 0 1010100 + 0 ack data ack 7 bit physical address + (w) bit 0 ack 0xxxxxxx sub-address (msb=0) 0 xxxxxxxx 0 1010100 + 0 ack data ack 7 bit physical address + (w) bit start bit end bit 1 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 1 1 ack ack ack figure 7. writing sequence i 2 c bit stream ? rs 1 7 bit physical add + (w) bit sub-address (msb=1) ack a ck a ck a ck ph ysical a dd + ( r ) bit data read 1010100 + 0 1xxxxxxx 1010100 + 1 0 0 0 1 xxxxxxx 1 0 1 0 1 0 0 1 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0 1 1 1 1 1 start bit a ck ack a ck a ck end bit rs figure 8. reading sequence i 2 c bit stream user programmable registers grpc/e power sequencing setting (34704a only) the microprocessor can choose one of several voltage sequ ence options for the grpc/e supply (reg5), high voltage supply (reg6), and negative voltage supply (reg7). for 3 of the sequencing options, reg5 supply is controlled and tied with reg6 and reg7 in a preset power sequence. by default, only reg6 and reg7 are involved in the power sequence and reg5 is independently controlled with grpe. 34704a assigns 2 bits to program the grpc/e power sequ encing options ( ccdseq[1:0] ). these bits value is latched in at grpc power up and will not be allowed to change unless a power recycle happens. option msb lsb grpc/e enabled grpc/e disabled 1 (default) 0 0 reg5 is independently controlled reg6 and reg7 ramp up together. reg5 is independently controlled reg6 and reg7 ramp down together
analog integrated circuit device data 32 freescale semiconductor 34704 functional device operation logic commands and registers switching frequency for reg6, 7 & 8 f sw2 can be selected to be between 250 khz and 1.0 mhz in 25 0 khz steps. on the 34704b, fsw2 is just for reg8 since reg6 and 7 do not exist in this device. 34704 assigns 2 bits to program f sw2 ( f sw2 [1:0] ) fsw2 msb lsb 500khz (default) 0 0 250khz 0 1 750khz 1 0 1000khz 1 1 shutdown hold (delay) time the 34704 assigns 2 bits ( sddelay[1:0] ) for the processor to program the shutdown delay time period shutdown delay msb lsb 1.0sec (default) 0 0 0.5sec 0 1 1.5sec 1 0 2.0sec 1 1 please refer to the /onoff pin description for more details programming 34704 response to under-voltage/over- vo ltage conditions on each regulator there are two responses that can be prog rammed for an over-voltage/under-voltage condition: response a : w hen an over-voltage (under-voltage) event is detected, the concerned out put shuts down and a register is flagged to alert the processor. response b : wh en an over-voltage/under-voltage event is detected, the concerned out put will not shutdown, but the register is flagged to alert th e processor. then, the processor can decide whether to shutdown the output or not. in the mean time, the concerned output control loop will be attempting to correct the error. see output over-voltage/under-voltage monitoring on page 30 for more details. response a and response b share the same flag bit 34704 assigns 1 bit for this function ( ovuvsetx ) w here x corresponds to each regulator. ov/uv response bit a (default) 0 b 1 dynamic voltage scaling for each regulator the customer can adjust each regulator?s output dyna mically with 2.5% step size. the total range of adjustability will vary depending on each regulator to accommodate different operating environments. some regulators will utilize the full range of -20.00% to +17.50% and some regulators will only use the range of 10.00%. for details, see each regulator?s se ction. each 2.5% step takes 50 s before moving to the next step. reg8 only performs dvs when in voltage regulation mode. during dvs, the over-voltage and under-voltage moni toring will not be active. in addition to that, these faults will be masked and not active for a dvs settling time period equal to 1ms. this dvs settling time will start after the dvsstat register is flagged indi cating that the dvs cycle is done. this is to ensure that during dvs and soft start alike the output will not be tripped due to a momentary over- voltage or under-voltage fault. this is the same for response a and response b of the over-v oltage/under-voltage fault monitoring. 34704 assigns 4 bits register to program the dynamic voltag e scaling for each regulator ( dvssetx[3:0] ) where x corresponds to each regulator. 2 0 1 reg5 ramps up first then reg6 and reg7 ramp up together reg5, reg6 and reg7 ramp down together 3 1 0 reg5, reg6, and reg7 ramp up together reg5, reg6, and reg7 ramp down together 4 1 1 reg5 and reg6 ramp up together first. then ramp up reg7 reg7 ramps down first. then reg5 and reg6 ramp down together option msb lsb grpc/e enabled grpc/e disabled
percentage change msb lsb 0.00% (default) 0 0 0 0 +2.50% 0 0 0 1 +5.00% 0 0 1 0 +7.50% 0 0 1 1 +10.00% 0 1 0 0 +12.50% 0 1 0 1 +15.00% 0 1 1 0 +17.50% 0 1 1 1 -20.00% 1 0 0 0 -17.50% 1 0 0 1 -15.00% 1 0 1 0 -12.50% 1 0 1 1 -10.00% 1 1 0 0 -7.50% 1 1 0 1 -5.00% 1 1 1 0 -2.50% 1 1 1 1 analog integrated circuit device data freescale semiconductor 33 34704 functional device operation logic commands and registers on/off control for each group of regulators as defined previously and for the whole ic 34704 assigns 1 bit per group to turn each group on/off (onoffa, c, d, or e bits). pl ease note that grpb does not have a dedicated enable register which is enabled by default. grpa, c, d, or e onoff bit off (default) 0 on 1 also, 34704 assigns 1 bit (alloff) for disabling the whole ic through the i 2 c. ( alloff bit ) all off bit false (default) 0 true 1 soft start time there are two set of bits for se tting the soft start value for all of the regulators except reg1. the sstime[1:0] bits reads the soft start value set by the ss pin and is used to initially set the soft start value for all of the regulators except reg1. then, the ssset bits fo r reg5 through reg8 can be used to change the soft start value for these regulators from the value set by the sstime. here is how the sstime bi ts interacts with the sssetx register bits: 1. sstime is set by a value read through the ss pin. 2. sstime is copied into the bit s ssset5, ssset6, ssset7, and ssset8. 3. the soft start time of reg2, reg3, and reg4 are only af fected by the value of sstime bits. 4. the soft start time of reg5, reg6, reg7, and reg8 are af fected by the value of bits ssset5, ssset6, ssset7, and ssset8 respectively. 34704 assigns 2 bits to store the value programmed by the ss pin. bits sstime[1:0] can only be read by the user. soft start msb lsb 0.5ms 0 0 2ms 0 1 8ms 1 0 32ms 1 1 34704 assigns 2 bits for reg5 through reg8 to program the soft start times for these regulators ( sssetx[1:0] ) where x corresponds to each regulator from reg5 through reg8. soft start msb lsb 0.5ms 0 0 2ms 0 1 8ms 1 0 32ms 1 1 reg8 regulation mode the 34704 assigns 1 bit to indicate reg8?s regulation mode ( reg8mode ). the processor assigns this bit to either regulation mode before enabling the reg8 output. reg8 regulation bit current (default) 0 voltage 1 when reg8 is current regulated, led backlight current can be reduced from the maximum in 16 steps through the i 2 c interface the maximum led current can be set using the external resistor at the bottom of the led string, then through i 2 c programming, this current value can be reduced in 16 steps. 34704 assigns 4 bits for this function ( iled[3:0] ) the iled setting is not a gua ranteed characteristic from i max * (1/16) to i max * (9/16), due to an error amp common mode limitation.
led current msb lsb i max * (1/16) 0 0 0 0 i max * (2/16) 0 0 0 1 i max * (3/16) 0 0 1 0 i max * (4/16) 0 0 1 1 i max * (5/16) 0 1 0 0 i max * (6/16) 0 1 0 1 i max * (7/16) 0 1 1 0 i max * (8/16) 0 1 1 1 i max * (9/16) 1 0 0 0 i max * (10/16) 1 0 0 1 i max * (11/16) 1 0 1 0 i max * (12/16) 1 0 1 1 i max * (13/16) 1 1 0 0 i max * (14/16) 1 1 0 1 i max * (15/16) 1 1 1 0 i max (default) 1 1 1 1 analog integrated circuit device data 34 freescale semiconductor 34704 functional device operation logic commands and registers accurate i 2 c communication mode the 34704 assigns 1 bit to enable the accurate i 2 c communication mode (accurate). setting this bit enables the accurate mode in which each command and data should be sent 2 times to avoid false commands. user accessible flag registers cold start flag the 34704 assigns 1 bit ( col df ) to flag the processor that the power up was a result of battery insertion and not through onoff pin. this flag should be cleared after power up by the processor. cold start flag bit /onoff (default) 0 battery insertion 1 shutdown flag the 34704 assigns 1 bit ( shutd own ) to flag the processor if a shutdown signal is received through the onoff pin and a programmable time period with a default of 1sec has elapsed. /onoff status bit normal (default) 0 shutdown 1 dynamic voltage scaling status flag in addition and for each regulator, 34704 assigns 1 bit (dvsstatx) to flag to the proce ssor that the desired output voltage level set with the dvssetx bits has been reached. dvs status bit dvs not done 0 dvs done 1 user accessible fault registers over-current fault register the 34704 assigns 1 bit for each regulator ( ilimf x ) to indicate a fault due to over-current limit, where x corresponds to each regulator from reg1 to reg8, except reg7 ilimf bit false 0 true 1 short-circuit fault register the 34704 assigns 1 bit for each regulator ( scfx ) to in dicate a fault due to short-circuit current limit, where x corresponds to each regulator from reg1 to reg8, except reg7 scf bit false 0 true 1 over-voltage fault register the 34704 assigns 1 bit for each regulator ( ovf x ) to indicate a fault due to over-voltage limit, where x corresponds to each regulator from reg1 to reg8 ovf bit false 0 true 1 under-voltage fault register the 34704 assigns 1 bit for each regulator ( uvf x ) to indicate a fault due to under-voltage limit, where x corresponds to each regulator from reg1 to reg8. uvf bit false 0 true 1 thermal shutdown fault register
analog integrated circuit device data freescale semiconductor 35 34704 functional device operation logic commands and registers the 34704 assigns 1 bit for each regulator ( tsdfx ) to indicate a fault due to thermal limit, where x corresponds to each regulator from reg1 to reg8, except reg7 tsdf bit false 0 true 1 regulator fault register the 34704 assigns 1 bit for each regulator ( faul tx ) to indicate that a fault had occurred on each regulator. the processor can just access this register periodically to determine system status. this reduces the access cycles. if a regulator fault register asserted, then the processor can access that regulator?s registers to see what kind of fault had occurred. fault bit false 0 true 1 special registers reg3 fine voltage scaling register regulator 3 has an additional fine output voltage scaling th at enables to lower the out put voltage in 0.5% steps. the 34704 assigns an 8-bit register (reg3dac) to the reg3 digital to analog converter for the fb3 voltage generation. output votlage must be reduced gradually to avoid a ov/uv fault to occur. reg7 independent on/off control (only on 34704a) the 34704b provide two register to independently turn on reg7 when reg6 is not needed. care must be taken when turning on reg7 to avoid inrush currents during regulator ramp-up. following process must be followed to assure successful turn on of reg7. 1. set en0 and clear dischr_b on reg7cr0 register 2. after 1ms or more, set en1 on reg7cr0 register 3. set reg7dac register to $00 4. gradually shift up reg7dac register from $00 to $d9 to ra mp-up the output voltage in a soft-start like wave. soft start timing is dependant of i2c communication speed and number of bit you change per writing, for instance use 4,8 or 16 bits increase to ramp up the output voltage. register address code 1 $58 $50 2 $58 $d0 3 $59 $00 4 $59 $04 5 $59 $08 6 $59 $0c ... ... ... 55 $59 $d9 reg7 independent start up example register descript ion summary table register addr r/w bit name bits description general1 $01 r/w ccdseq 1:0 grpc/e power sequence selection sddelay 3:2 hard shutdown delay timer selection general2 $02 r/w onoffx 3:0 grpa,c,d,e on/off bits alloff 4 soft shutdown bit (turn off all regulators) general3 $03 r sstime 1:0 soft start configuration latch r/w coldf 3 cold power up detection flag r/w shtd 4 hard shutdown detection flag vgset1 $04 r/w ovuvset1 0 set reg1/vg response type to ov/uv r/w dvsset1 4:1 reg1 dvs value setting vgset2 $05 r dvsstat1 0 dvs voltage level status flag r - 5:1 reg1 fault flags: thermal sd, sc, ilim, uv and ov reg2set1 $06 r/w ovuvset2 0 set reg2 response type to ov/uv r/w dvsset2 4:1 reg2 dvs value setting
analog integrated circuit device data 36 freescale semiconductor 34704 functional device operation logic commands and registers reg2set2 $07 r dvsstat2 0 dvs voltage level status flag r - 5:1 reg2 fault flags: thermal sd, sc, ilim, uv and ov reg3set1 $08 r/w ovuvset3 0 set reg3 response type to ov/uv r/w dvsset3 4:1 reg3 dvs value setting reg3set2 $09 r dvsstat3 0 dvs voltage level status flag r - 5:1 reg3 fault flags: thermal sd, sc, ilim, uv and ov reg4set1 $0a r/w ovuvset4 0 set reg4 response type to ov/uv r/w dvsset4 4:1 reg4 dvs value setting reg4set2 $0b r dvsstat4 0 dvs voltage level status flag r - 5:1 reg4 fault flags: thermal sd, sc, ilim, uv and ov reg5set1 $0c r/w ovuvset5 0 set reg5 response type to ov/uv r/w dvsset5 4:1 reg5 dvs value setting reg5set2 $0d r/w ssset5 1:0 reg5 soft start setting. reg5set3 $0e r dvsstat5 0 dvs voltage level status flag r - 5:1 reg5 fault flags: thermal sd, sc, ilim, uv and ov reg6set1 $0f r/w ovuvset6 0 set reg6 response type to ov/uv r/w dvsset6 4:1 reg6 dvs value setting reg6set2 $10 r/w ssset6 1:0 reg6 soft start setting. reg6set3 $11 r dvsstat6 0 dvs voltage level status flag r - 5:1 reg6 fault flags: thermal sd, sc, ilim, uv and ov reg7set1 $12 r/w ovuvset7 0 set reg7 response type to ov/uv r/w dvsset7 4:1 reg7 dvs value setting reg7set2 $13 r/w ssset7 1:0 reg7 soft start setting. r/w fsw2 3:2 reg6, 7 8, frequency setting reg7set3 $14 r dvsstat7 0 dvs voltage level status flag r - 2:1 reg7 fault flags: uv and ov reg8set1 $15 r/w ovuvset8 0 set reg8 response type to ov/uv r/w dvsset8 4:1 reg8 dvs value setting reg8set2 $16 r/w ssset8 1:0 reg8 soft start setting. r/w reg8mode 3:2 voltage or current regulation mode on reg8 r/w iled 6:4 led string current configuration during current regulation mode reg8set3 $17 r dvsstat8 0 dvs voltage level status flag r - 5:1 reg8 fault flags: thermal sd, sc, ilim, uv and ov faults $18 r fltx 7:0 first level fault register for reg1 through reg8 i2cset1 $19 r/w accurate 0 accurate i2c communication mode enable reg3dac $49 r/w 3dacx 7:0 reg3 dac reference voltage configuration for fine voltage scaling reg7cr0 $58 r/w dischg_b 4 discharge enable for independent reg7 control r/w en 7:6 output enable bits for independent reg7 control reg7dac $59 r/w 7dacx 7:0 reg7 dac refence voltage configuration for reg7 control register addr r/w bit name bits description
analog integrated circuit device data freescale semiconductor 37 34704 functional device operation logic commands and registers i 2 c register distribution each regulator has a fault register that records any fault that occurs in that regulator. then there is a regulator fault reporting register th at the processor can access at all times to see if any fault had occurred. there are also the ic general use registers. those regi sters are also split between status reporting registers and processor programmable registers. this distribution keeps each re gulator?s registers bundled together which makes it easier for the user to access one regulator at a time. addr name d7 d6 d5 d4 d3 d2 d1 d0 $00 reserved - $01 general1 - sddelay[1:0] ccdseq[1:0] $02 general2 - alloff onoffa onoffc onoffd onoffe $03 general3 - shtd coldf - sstime[1:0] $04 vgset1 - dvsset1[3:0] ovuvset1 $05 vgset2 - tsdf1 scf1 ilimf1 uvf1 ovf1 dvsstat1 $06 reg2set1 - dvsset2[3:0] ovuvset2 $07 reg2set2 - tsdf2 scf2 ilimf2 uvf2 ovf2 dvsstat2 $08 reg3set1 - dvsset3[3:0] ovuvset3 $09 reg3set2 - tsdf3 scf3 ilimf3 uvf3 ovf3 dvsstat3 $0a reg4set1 - dvsset4[3:0] ovuvset4 $0b reg4set2 - tsdf4 scf4 ilimf4 uvf4 ovf4 dvsstat4 $0c reg5set1 - dvsset5[3:0] ovuvset5 $0d reg5set2 - ssset5[1:0] $0e reg5set3 - tsdf5 scf5 ilimf5 uvf5 ovf5 dvsstat5 $0f reg6set1 - dvsset6[3:0] ovuvset6 $10 reg6set2 - ssset6[1:0] $11 reg6set3 - tsdf6 scf6 ilimf6 uvf6 ovf6 dvsstat6 $12 reg7set1 - dvsset7[3:0] ovuvset7 $13 reg7set2 - fsw2[1:0] ssset7[1:0] $14 reg7set3 - uvf7 ovf7 dvsstat7 $15 reg8set1 - dvsset8[3:0] ovuvset8 $16 reg8set2 - iled[3:0] reg8mode ssset8[1:0] $17 reg8set3 - tsdf8 scf8 ilimf8 uvf8 ovf8 dvsstat8 $18 faults flt8 flt7 flt6 flt5 flt4 flt3 flt2 flt1 $19 i2cset1 - accurate $49 reg3dac 3dac7 3dac6 3dac5 3dac4 3dac3 3dac2 3dac1 3dac0 $58 reg7cr0 en[1:0] - dischg_b - $59 reg7dac 7dac7 7dac6 7dac5 7dac4 7dac3 7dac2 7dac1 7dac0 34704a register distribution map
addr name d7 d6 d5 d4 d3 d2 d1 d0 $00 reserved - $01 general1 - sddelay[1:0] - $02 general2 - alloff - - onoffd onoffe $03 general3 - shtd coldf - sstime[1:0] $04 reserved - $05 vgset2 - - - - uvf1 ovf1 - $06 reg2set1 - dvsset2[3:0] ovuvset2 $07 reg2set2 - tsdf2 scf2 ilimf2 uvf2 ovf2 dvsstat2 $08 reg3set1 - dvsset3[3:0] ovuvset3 $09 reg3set2 - tsdf3 scf3 ilimf3 uvf3 ovf3 dvsstat3 $0a reg4set1 - dvsset4[3:0] ovuvset4 $0b reg4set2 - tsdf4 scf4 ilimf4 uvf4 ovf4 dvsstat4 $0c reg5set1 - dvsset5[3:0] ovuvset5 $0d reg5set2 - ssset5[1:0] $0e reg5set3 - tsdf5 scf5 ilimf5 uvf5 ovf5 dvsstat5 $0f- $12 reserved - $13 fsw2set - fsw2[1:2] - $14 reserved - $15 reg8set1 - dvsset8[3:0] ovuvset8 $16 reg8set2 - iled[3:0] reg8mode ssset8[1:0] $17 reg8set3 - tsdf8 scf8 ilimf8 uvf8 ovf8 dvsstat8 $18 faults flt8 - - flt5 flt4 flt3 flt2 flt1 $19 i2cset1 - accurate $49 reg3dac dac7 dac6 dac5 dac4 dac3 dac2 dac1 dac0 $58 reg7cr0 en[1:0] - dischg_b - $59 reg7dac 7dac7 7dac6 7dac5 7dac4 7dac3 7dac2 7dac1 7dac0 34704b register distribution map analog integrated circuit device data 38 freescale semiconductor 34704 functional device operation logic commands and registers
analog integrated circuit device data freescale semiconductor 39 34704 functional device operation component calculation component calculation f sw1 and general soft start configuration the 34704 uses f sw1 as the switching frequency for reg1(vg) thru reg5, and this can be changed by applying a voltage between 0 to 2.5 v to the freq pin. if the freq pin is left unconnected, the 34704 starts up with a default frequency of 750 khz. to configure the f sw1 , use a 2 resistors voltage divider from vddi to ground to set the voltage on the freq pin as indicated bellow: ratio f sw1 [khz] 0 750 9/32 1000 13/32 1250 17/32 1500 21/32 1750 vddi 2000 notes 27. if an external voltage is used, f sw1 can only be set during device startup. vddi gnd freq rf1 rf2 v freq v ddi rf2 rf1 rf2 + ------------------------------ ?? ?? = v freq rf1, rf2 tolerance 1.0% initially at power up, the soft st art time will be set for all of the regulators through programming the ss pin with an external resistor divider con nected between vddi and agnd as follows: ratio soft start timing [ms] 0 0.5 11/32 2.0 19/32 8.0 vddi 32.0 i dd max = 100 ? vddi gnd ss rss1 rss2 v ss v ddi rss2 rss1 rss2 + --------------------------------------- - ?? ?? = v ss rss1, rss2 tolerance 1.0% regulators power stage and compensation calculation regulator 1 and 6 (synchronous boost - internally compensated - reg1 is vg supply). reg1 is a synchronous boost converter set to 5.0 v and maximum current of 500 ma while reg6 is set to 15 v at 60 ma (on the 34704b, reg1 does not exist but similar circuitry is u sed to provide the internal vg voltage). they do not need an external compensatio n network, thus, the only components that need to be calculated are: ? r1 a nd rb (only reg6): these two resistors help to set the output voltage to the desi re value using a vref=0.6 v, sele ct r1 between 10 k and 100 k and then calculate rb as fo llows: rb r1 vo vref ----------- - 1? --------------------- - = [ ] ? l : a boost power stage can be designed to operate in ccm for load currents above a certain level usually 5 to 15% of full load. the minimum value of inductor to maintain ccm can be determined by using the following procedure:
analog integrated circuit device data 40 freescale semiconductor 34704 functional device operation component calculation 1. define i ob as the minimum current to maintain ccm as 15% of full load. l min vo d () 1d ? () 2 t 2i ob ------------------------------------------ - (h) where: d = dutycycle vo = output voltage t = switching period iob = boundary current to achieve ccm 2. however the worst case c ondition for the boost power stage is when the input voltage is equal to one half of the output voltage, which results in the maximum i l , then: l min vo t () 16i ob ---------------- (h) note: on the 34704b use the recommended 3.0uh inductor rated between 50 to 100 ma in order to have this regu lator working in dcm. rising the inductor value will make the regulator to begin working in ccm. ? c out : the three elements of output capacitor that contribute to its impedance and output voltage ripple are the esr, the esl and the capacitance c. the minimum capacitor value is approximately: c out io max d max fsw vo r ----------------------------- (f) where: dmax = maximum dutycycle fsw = switching frequency ?where vo r is the desired output voltage ripple. ? now calculate the maximum allowed esr to reach the desi red vo r . esr vo r io max 1d max ? ----------------------- i ob + ?? ?? -------------------------------------------- - [ ] ? 1cvg (only reg1) : use a 47uf capacitor from ground to vg. ? d1 (o nly reg1) : use a fast recovery schottky diode rated to 10v at 1a. regulator 2, 4 and 5 (synchronous buck-boost regulator with ex ternal compensation) these three regulators are 4 -switch synchronous buck- boost voltage mode control dc-dc regulator that can operate at various output voltage levels. since each of the regulators may work as a buck or a boost depending on the operating voltages, t hey need to be compensated in different ways for each situation. since the 34704 is meant to work using a liion battery, the op erating input voltage range is set from 2.7 - 4.2 v, then the follo wing scenarios are possible: regulator vo input voltage range operation 2 2.8 v 3.0 - 4.2 buck 3.3 v 2.7 - 3.0 boost 3.3 v 3.5 - 4.2 buck 4 1.8 v 2.7 - 4.2 buck 2.5 v 2.7 - 4.2 buck 5 3.3 v 2.7 - 3.0 boost 3.3 v 3.5 - 4.2 buck ? note: since these 3 regulators can work as a buck or a boost in a single application, a good practice to configure these regulators is to compensate for a boost scenario and then verify that the regulator is working in buck mode using that same compensation. compensating for buck operation: ? l: a buck power stage can be designed to operate in ccm for load currents above a certain level usually 5 to 15% of full load. the minimum value of inductor to maintain ccm can be determined by using the following procedure: 1. define i ob as the minimum current to maintain ccm as 15% of full load. l min vo ( io max +r dsonlsfet r l + () d min ) t 2i ob --------------------------------------------------------------------------------------------------------------------------- d max t vo 2i ob -------------- [h] where: rdsonlsfet = body resistance of the lowside fet rl = inductor winding resistance d'min = minimum off percentage given by 1- (vin_min/vout_max) d'max = maximum off percentage given by 1- (vin_max/vout_min) ? c out : the three elements of output capacitor that contribute to its impedance and output voltage ripple are the esr, the esl and the capacitance c. a good approach to calculate the minimum real capacitance needed is to include the transient response analysis to control the maximum overshoot as desired.
analog integrated circuit device data freescale semiconductor 41 34704 functional device operation component calculation 1. first calculate the dt_i (inductor current rising time) given by: dti io max t iostep --------------------- - = [s] where the parameter io_step is the maximum current step during the current rising time and is define as: iostep d max fsw ------------- - ?? ?? vin min vo ? l ------------------------------- ?? ?? = [a] 2. then the output capacitor can be chosen as follow: c out io max dti vo max ---------------------- [a] ?where vo max is the maximum allowed transient overshoot expressed as a percentage of the output voltage, typically from 3 to 5% of vo. 3. finally find the maximum allowed esr to allow the desi red transient response: esr max vo r fsw () l () vo 1 d min ? () -------------------------------------- = [ ] note: do not use the parameters vo r and vo max indistinctly, the first one indicates the output voltage ripple, while the second one is the maximum output voltage overshoot (transient response). ? r1 and rb: th ese two resistors help to set the output voltage to the desire value using a vref=0.6 v, select r1 be tween 10 k and 100 k and then calculate rb as follows: rb r1 vo vref ----------- - 1? --------------------- - = [ ] ? compensation network. (c1,c2,c3, r2, r3): for compensating a buck converte r, 3 important frequencies referring to the plant are: 1. output lc filter cutoff frequency (f lc ): f lc 1 lc out 2 -------------------------- = [hz] 2. cutoff frequency due to capacitor esr: f esr 1 2 c out () esr ---------------------------------------- = [hz] 3. crossover frequency (or bandwidth): f bw f sw 10 ----------- = [hz] the type 3 external compensation network will be in charge of canceling some of these poles and zeros to achieve stability in the syst em. the following poles and zeroes frequencies are provided by the type 3 compensation.
f po f bw =f z1 0.9f lc =f 22 1.1f lc = analog integrated circuit device data 42 freescale semiconductor 34704 functional device operation component calculation f p1 f esr =f 2p f sw 2 ----------- = the passive components associated to these fre quencies are calculated with the following formulas. c1 vin min v ramp ------------------ 1 d min 2 ---------------- - ?? ?? ?? 1 2 f po r1 () ------------------------------- ?? ?? = c2 1 2 f z2 r1 () ----------------------------- - ?? ?? = r2 1 2 f z1 c1 () ----------------------------- - ?? ?? = r3 1 2 f p1 c2 () ------------------------------ ?? ?? = c3 1 2 f p2 r2 () ------------------------------ ?? ?? = on the 34704 v ramp is half of 1.2 v since each operation mode spen ds only half the ramp.
analog integrated circuit device data freescale semiconductor 43 34704 functional device operation component calculation compensating for boost operation: ? l: a boost power stage can be designed to operate in ccm for load currents above a certain level usually 5 to 15% of full load. the minimum value of inductor to maintain ccm can be determined by using the following procedure: 1. define i ob as the minimum current to maintain ccm as 15% of full load: l min vo d () 1d ? () 2 t 2i ob ------------------------------------------ - [h] however the worst case cond ition for the boost power stage is when the input voltage is equal to one half of the output voltage, which results in the maximum i l , then: l min vo t () 16i ob ---------------- [h] ? cout: the three elements of output capacitor that contribute to its impedance and output voltage ripple are the esr, the esl and the capacitance c. the minimum capacitor value is approximately: c out io max d max fsw vo r ----------------------------- [f] ?where vo r is the desired output voltage ripple. ? now calculate the maximum allowed esr to reach the desi red vo r : esr vo r io max 1d max ? ----------------------- i ob + ?? ?? -------------------------------------------- - [ ] ? r1 and rb: these two resistors help to set the output voltage to the desi re value using a vref=0.6v, select r1 between 10k and 100k and then calculate rb as follows: rb r1 vo v ref ------------- - 1? ----------------------- - = [ ] ? compensation network. (c1,c2,c3, r2, r3) for compensating a boost converter, 4 important fre quencies referring to the plant are: 1. output lc filter cutoff frequency (f lc ): f lc d min lc out 2 -------------------------- = [hz] ?where d? min is the minimum off time percentage given by: d min vin min vout max ---------------------- - = 2. cutoff frequency due to capacitor esr: f esr 1 2 c out () esr ---------------------------------------- = [hz] 3. the right plane zero frequency: rhp z d min () 2 r load 2 l ---------------------------------------- - = [hz] 4. crossover frequency (or bandwidth): select this frequency as far away form the rhp z as much as possible: f bw rhp z 6 --------------- - ? [hz] the type 3 external compensation network will be in charge of canceling some of these poles and zeros to achieve stability in the syst em. the following poles and zeroes frequencies are provided by the type 3 compensation: f po f bw =f z1 0.9f lc =f 22 1.1f lc = f p1 f esr =f 2p f sw 2 ----------- =
analog integrated circuit device data 44 freescale semiconductor 34704 functional device operation component calculation the passive components associated to these fre quencies are calculated with the following formulas c1 vin min v ramp ------------------ 1 d min 2 ---------------- - ?? ?? ?? 1 2 f po r1 () ------------------------------- ?? ?? = c2 1 2 f z2 r1 () ----------------------------- - ?? ?? = r2 1 2 f z1 c1 () ----------------------------- - ?? ?? = r3 1 2 f p1 c2 () ------------------------------ ?? ?? = c3 1 2 f p2 r2 () ------------------------------ ?? ?? = on the 34704 v ramp is half of 1.2 v since each operation mode spen ds only half the ramp. regulator 3 (synchronous buck - internally co mpensated) ? l: a buck power stage can be designed to operate in ccm for load currents above a certain level usually 5 to 15% of full load. the minimum value of inductor to maintain ccm can be determined by using the following procedure: 1. define i ob as the minimum current to maintain ccm as 15% of full load. l min vo io max + ( r dsonlsfet r l + () d min () t 2i ob ------------------------------------------------------------------------------------------------------------- - l min d t vo 2i ob ------------ [h] ? c out : the three elements of output capacitor that contribute to its impedance and output voltage ripple are the esr, the esl and the capacitance c. a good approach to calculate the minimum real capacitance needed is to include the transient response analysis to control the maximum overshoot as desired. ? first calculate the dt_ i (inductor current rising time) given by: dti io max t iostep --------------------- = [s] where the parameter io _ step is the maximum current step during the current rising time and is define as: iostep d max fsw ------------- - ?? ?? vin min vo ? l ------------------------------- ?? ?? = [a] ? then the output capacitor can be chosen as follow: c out io max dti vo max ---------------------- [f] where vo max is the maximum allowed transient overshoot expressed as a percent age of the output voltage, typically from 3 to 5% of vo. ? finally find the maximum allowed esr to allow the de sired transient response: esr max vo r fsw () l () vo 1 d min ? () -------------------------------------- = [ ] note: do not use the parameters vo r and vo max indistinctly, the first one indicates the output voltage rip - ple, while the second one is the maximum output volt - age overshoot (transient response). ? r1 and rb: th ese two resistors help to set the output voltage to the desire value using a v ref =0.6 v, select r1 be tween 10 k and 100 k and then calculate rb as follows: rb r1 vo vref ----------- - 1? --------------------- - = [ ] regulator 8 (synchronous boost - in ternally compensated -voltage or current feedback) reg8 is a synchronous boost converter set to 15v with a maximum current of 30 ma and can be used with voltage
analog integrated circuit device data freescale semiconductor 45 34704 functional device operation component calculation feedback using the standard voltage divider configuration, or can be programmed to work with a current feedback configuration to control the current flowing through a led string. it does not need external compensation network, thus the only components that need to be calculated are: ? l : a boost power stage can be designed to operate in ccm for load currents above a certain level usually 5 to 15% of full load. the minimum value of inductor to maintain ccm can be determined by using the following procedure: ?define i ob as the minimum current to maintain ccm as 15% of full load: l min vo d () 1d ? () 2 t 2i ob ------------------------------------------ - [h] however the worst case cond ition for the boost power stage is when the input voltage is equal to one half of the output voltage, which results in the maximum ?i l , then: l min vo t () 16i ob ---------------- [h] ? c out : the three elements of output capacitor that contribute to its impedance and output voltage ripple are the esr, the esl and the capacitance c. the minimum capacitor value is approximately: c out io max d max fsw vo r ----------------------------- [f] ?where vo r is the desired output voltage ripple. ? now calculate vo r the maximum allowed esr to reach the desired. esr vo r io max 1d max ? ----------------------- i ob + ?? ?? -------------------------------------------- - [ ] ? r1 and rb (for voltage feedback control): these two resistors help to set the output voltage to the desire value using a v ref =0.6 v, select r1 between 10k and 100k and th en calculate rb as follows: rb r1 vo vref ----------- - 1? --------------------- - = [ ] ? rs (for current feedback control with led string): this resistor is attached at th e end of the led string and it controls the amount of curr ent flowing through it. to calculate this resistor, set the maximum current you want to flow though the string and use the following formula: rs v ref io --------- - = [ ] where v ref =230 mv is the maximum internal reference voltag e in current mode control that is reflected on the fb8 pin. when input voltage is equal to or higher than vout8, a reverse bias diode is needed from the switching node to the output in order to cause a drop from the input to the output, see figure 9 below: l8 cboot r1 rb vout8 vin d8 bt8 sw8 vout8 fb8 figure 9. reverse bias diode regulator 7 (inverter controller - external compensation ne eded) reg7 is a non-synchronous buck/boost inverting pwm voltag e-mode control dc-dc regula tor that drive an external p-mosfet to supply a typical voltage of -7.0 v at a maximum current of 60 ma. ? p-mosfe t: the peak current of the mosfet is assumed to be i d , which is obtained by the following formula, define i ob from 5 to 15% of maximum current rating. i q i lpeak io i ob + () ? 1d ? ---------------------------- - = and the voltage rating is given by: v q vin vo ?= ? diode d7: the peak value of the diode current is i fsm which should also be higher than i lpeak . the average current rating should be higher than the output current low and the repetition reverse voltage v rrm is given by:
v rrm vin vo ? analog integrated circuit device data 46 freescale semiconductor 34704 functional device operation component calculation ? l: the minimum value of inductor to maintain ccm can be determined by using the following procedure: l min vot ? 2io max ------------------ vin min vo vin min ? ------------------------------- ?? ?? 2 [h] ? c out : the three elements of output capacitor that contribute to its impedance and output voltage ripple are the esr, the esl and the capacitance c. the minimum capacitor value is approximately: c out io max d max f sw vo r ----------------------------- [f] ?where vo r is the desired output voltage ripple. ? now calculate the maximum allowed esr to reach the desi red. [ ] esr vo r io max 1d max ? ----------------------- i ob 1d ? ------------- - + ?? ?? ------------------------------------------------- - ? r1 and rb: these two resistors help to set the output voltage to the desire value using a v fb 7=0.6v, select r1 between 10 k and 150 k and then calculate rb as follows: [ ] rb 0.9 1.5 vo ?0.9 ? ------------------------------------ - r1 = note: rb is not grounded, instead is connected to vref7 pin (vref7=1.5 v) which provide a positive voltage to assure a positive voltage at the fb7 pin. ? compensation network. (c1,c2,c3, r2, r3) for compensating a buck converter, 4 important fre quencies referring to the plant are: ? output lc filter cutoff frequency (f lc ): [hz] f lc d min lc out 2 -------------------------- = where d? min is the minimum off time percentage given by: d min vin min vout max ------------------------- - = ? cutoff frequency due to capacitor esr: f esr 1 2 c out () esr ---------------------------------------- = [hz] ? the right plane zero frequency: [hz] rhp z d min () 2 r load d2 l ? ---------------------------------------- - = ? crossover frequency (or bandwidth): select this frequency as far away form the rhp z as much as possible: [hz] f bw rhp z 6 --------------- - ? the type 3 external compensation network will be in charge of canceling some of these poles and zeros to achieve stability in the syst em. the following poles and zeroes frequencies are provided by the type 3 compensation: f po f bw =f z1 0.9f lc =f 22 1.1f lc = f p1 f esr =f 2p f sw 2 ----------- =
analog integrated circuit device data freescale semiconductor 47 34704 functional device operation component calculation the passive components associated to these fre quencies are calculated with the following formulas. c1 vin min v ramp ------------------ 1 d min 2 ---------------- - ?? ?? ?? 1 2 f po r1 () ------------------------------- ?? ?? = c2 1 2 f z2 r1 () ----------------------------- - ?? ?? = r2 1 2 f z1 c1 () ----------------------------- - ?? ?? = r3 1 2 f p1 c2 () ------------------------------ ?? ?? = c3 1 2 f p2 r2 () ------------------------------ ?? ?? = on the 34704 v ramp is half of 1.2 v since each operation mode spen ds only half the ramp.
analog integrated circuit device data 48 freescale semiconductor 34704 typical applications typical applications v7 drv7 pvin5 sw6 vout7 sw5u vref7 fb7 comp7 vin bt3 pvin3 sw3 vout3 fb3 v3 fb8 v2 agnd vin scl sda rst vddi v2 bt2d pvin2 sw2d vout2 sw2u bt2u fb2 comp2 onoff vin reg8 reg3 reg2 vg reg7 vin 34704a vin vin vin vddi bt8 reg8 sw8 vin v6 bt6 fb6 sw5d vout6 vout5 bt5d fb5 comp5 vin reg6 vin vbus ss freq v8 vin bt5u v5 pgnd vg bt1 vout1 sw1 vin v1 reg5 pvin4 sw4u sw4d vout4 bt4d fb4 comp4 vin bt4u v4 reg4 (expad) notes 18. agnd(s) & pgnd(s) should be connected together as close to the ic as possible 19. refer to the fb8 functional pin description on page 17. (19) (18)
analog integrated circuit device data freescale semiconductor 49 34704 typical applications figure 10. 34704a typical application diagram v5 bt5d pvin5 sw5d vout5 sw5u bt5u fb5 comp5 vin bt3 pvin3 sw3 vout3 fb3 v3 fb8 v2 pgnd vin scl sda rst vddi agnd v2 bt1 bt2d pvin2 sw2d vout2 sw2u bt2u fb2 comp2 onoff vin vg sw1 reg8 reg3 reg2 vg reg5 vin vin 34704b vin vin vin vin bt8 reg8 sw8 vin v4 bt4d pvin4 sw4d vout4 sw4u bt4u fb4 comp4 vin reg4 vin vbus (expad) ss freq notes 20. agnd(s) & pgnd(s) should be connected to gether as close to the ic as possible 21. refer to the fb8 functional pin description on page 17. (21) (20) figure 11. 34704b typical application diagram
analog integrated circuit device data 50 freescale semiconductor 34704 packaging package dimensions packaging package dimensions for the most current package revision, visit www.freescale.com and perform a keyword search using the ?98a? listed below. ep suffix 56-pin 98asa10751d revision a
analog integrated circuit device data freescale semiconductor 51 34704 packaging package dimensions (continued) package dimensions (continued) ep suffix 56-pin 98asa10751d revision a
analog integrated circuit device data 52 freescale semiconductor 34704 packaging package dimensions (continued) package dimensions (continued) ep suffix 56-pin 98asa10751d revision a
analog integrated circuit device data freescale semiconductor 53 34704 revision history revision history revision date description of changes 2.0 4/2008 ? initial release 3.0 6/2008 ?revised 34704 simplified application diagram on page 1 ?revised 34704 internal block diagram on page 3 ?revised 34704 pin definitions on page 4 ?revised 34704a typical application diagram on page 49 and 34704b typical application diagram on page 49 4.0 6/2009 ? updated category from advance information to technical data. 5.0 1/2010 ? added max i 2 c speed as 400khz to dynamic elec trical characteristics table ? added device physical address to dynam ic e lectrical char acteristics table. ? added register definition summary table ? changed reg7 name definition on functional descr iption table to "inverter boost" ? added efficiency plots ? clarified grpc and e shutdown sequence ? clarified reg8 voltage/current reg ulation mode on feature list. ? clarified pulse skipping operation. ? added minimum fine scaling value at 40% ? correted register vs bit notation on i 2 c user interface section. ? added i 2 c reading and writing bit stream sequence example. ? added accurate bit definition ? revised pin definitions table for pins 3, 11, 35, 40, 46 and 53 ? removed li-ion battery references throughout document. ? added feedback reference voltage and feedback refe rence voltage on current regulation mode to table 4.
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